NDLI: From defects to failures: a view of dependable computing

Please wait, while we are loading the content...

Volume 16, Issue 5, Dec. 1988

Volume 16, Issue 4, Sept. 1988

Preface to the Special Issue on Architectural Support for Operating Systems

An intelligent memory system

The control mechanism for the Myrias parallel computer system

YACKOS on a shared-memory multiprocessor

Optimized communication in an extended remote procedure call model

Dynamic RAM for on-chip instruction caches

Modelling and performance evaluation of multiprocessors organization with shared memories

A survey of commercial parallel processors

Comparing production system architectures

The Flex architecture, a high speed graphics processor

An overview of the Kyushu University reconfigurable parallel processor

Some results concerning clock-regulated queues

Should SCC set condition codes?

A novel effective address calculation mechanism for RISC microprocessors

From defects to failures: a view of dependable computing

Book review: A VLSI Architecture for Concurrent Data Structures by William J. Dally (Kluwer 1988)

Book review: Computer Architecture and Organization, 2nd ed. by John P. Hayes (McGraw Hill, 1988)

Book review: Supercomputer Architectures by Paul B. Schneck (Kluwer Academic Publishers)

Volume 16, Issue 3, June 1988

Volume 16, Issue 2, May 1988

Volume 16, Issue 1, March, 1988

From defects to failures: a view of dependable computing

Content Provider	ACM Digital Library
Author	Parhami, Behrooz
Abstract	A unified framework and terminology for the study of computer system dependability is presented. Impairments to dependability are viewed from six abstraction levels. It is argued that all of these levels are useful, in the sense that proven dependability procurement techniques can be applied at each level, and that it is beneficial to have distinct, precisely defined terminology for describing impairments to and procurement strategies for computer system dependability at these levels. The six levels in the proposed framework are:1. Defect level or component level, dealing with deviant atomic parts.2. Fault level or logic level, dealing with deviant logic values or path selections.3. Error level or information level, dealing with deviant internal states.4. Malfunction level or system level, dealing with deviant functional behavior.5. Degradation level or service level, dealing with deviant performance.6. Failure level or result level, dealing with deviant outputs or actions.Briefly, a hardware or software component may be defective (perfect hardware may also become defective due to wear and aging). Certain system states expose the defect, resulting in the development of a logic-level fault. Information flowing within a faulty system may become contaminated, leading to the presence of an error. An erroneous system state may result in a subsystem malfunction. Automatic or manually controlled reconfiguration can isolate or bypass the malfunctioning subsystem but may lead to a degraded performance or service. Serious performance degradation may lead to a result-level system failure when untrustworthy or untimely results are produced. Finally, a failed computer system can have adverse effects on the larger societal or corporate system into which it is incorporated.
Starting Page	157
Ending Page	168
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/54331.54345
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	16
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in