NDLI: Trace preconstruction

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Volume 28, Issue 5, Dec. 2000

Volume 28, Issue 4, Sept., 2000

Volume 28, Issue 3, June 2000

Volume 28, Issue 2, May 2000

A scalable approach to thread-level speculation

Architectural support for scalable speculative parallelization in shared-memory multiprocessors

Transient fault detection via simultaneous multithreading

Trace preconstruction

Completion time multiple branch prediction for enhancing trace cache performance

A hardware mechanism for dynamic extraction and relayout of program hot spots

Energy-driven integrated hardware-software optimizations using SimplePower

A fully associative software-managed cache design

Recency-based TLB preloading

Memory access scheduling

Selective, accurate, and timely self-invalidation using last-touch prediction

An embedded DRAM architecture for large-scale spatial-lattice computations

Understanding the backward slices of performance degrading instructions

On the value locality of store instructions

Performance analysis of the Alpha 21264-based Compaq ES40 system

Reconfigurable caches and their application to media processing

Circuits for wide-window superscalar processors

Clock rate versus IPC

Vector instruction set support for conditional operations

Instruction path coprocessors

Allowing for ILP in an embedded Java processor

Early load address resolution via register tracking

Multiple-banked register file architectures

Volume 28, Issue 1, March 2000

Trace preconstruction

Content Provider	ACM Digital Library
Author	Jacobson, Quinn Smith, James E.
Abstract	Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due to capacity and compulsory misses. Trace preconstruction augments a trace cache by performing a function analogous to prefetching. The trace preconstruction mechanism observes the processor's instruction dispatch stream to detect opportunities for jumping ahead of the processor. After doing so, the preconstruction mechanism fetches static instructions from the predicted future region of the program, and constructs a set of traces in advance of when they are needed.Trace preconstruction can significantly increase both the performance of the trace cache and the robustness of the trace cache to varying workloads. All but one of the SPECint95 benchmarks see a notable reduction in trace cache miss rates from preconstruction. The three benchmarks that have the largest working set (gee, go and vortex) see a 30% to 80% reduction in trace cache misses. We also consider the integration of preconstruction with another trace-specific mechanism (preprocessing) to produce a high performance frontend. When combined, preconstruction and trace preprocessing produce an average speedup of 14% for the SPECint95 benchmarks.
Starting Page	37
Ending Page	46
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/342001.339653
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	28
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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