NDLI: Power challenges may end the multicore era

Please wait, while we are loading the content...

Power challenges may end the multicore era

Content Provider	ACM Digital Library
Author	Esmaeilzadeh, Hadi Burger, Doug Blem, Emily Amant, Renée St. Sankaralingam, Karthikeyan
Abstract	Starting in 2004, the microprocessor industry has shifted to multicore scaling---increasing the number of cores per die each generation---as its principal strategy for continuing performance growth. Many in the research community believe that this exponential core scaling will continue into the hundreds or thousands of cores per chip, auguring a parallelism revolution in hardware or software. However, while transistor count increases continue at traditional Moore's Law rates, the per-transistor speed and energy efficiency improvements have slowed dramatically. Under these conditions, more cores are only possible if the cores are slower, simpler, or less utilized with each additional technology generation. This paper brings together transistor technology, processor core, and application models to understand whether multicore scaling can sustain the historical exponential performance growth in this energy-limited era. As the number of cores increases, power constraints may prevent powering of all cores at their full speed, requiring a fraction of the cores to be powered off at all times. According to our models, the fraction of these chips that is "dark" may be as much as 50% within three process generations. The low utility of this "dark silicon" may prevent both scaling to higher core counts and ultimately the economic viability of continued silicon scaling. Our results show that core count scaling provides much less performance gain than conventional wisdom suggests. Under (highly) optimistic scaling assumptions---for parallel workloads---multicore scaling provides a 7.9× (23% per year) over ten years. Under more conservative (realistic) assumptions, multicore scaling provides a total performance gain of 3.7× (14% per year) over ten years, and obviously less when sufficiently parallel workloads are unavailable. Without a breakthrough in process technology or microarchitecture, other directions are needed to continue the historical rate of performance improvement.
Starting Page	93
Ending Page	102
Page Count	10
File Format	PDF
ISSN	00010782 15577317
DOI	10.1145/2408776.2408797
Journal	Communications of the ACM (CACM)
Volume Number	56
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-08-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article
Subject	Computer Science Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dark silicon and the end of multicore scaling

Power Limitations and Dark Silicon Challenge the Future of Multicore

Maximizing power efficiency with asymmetric multicore systems

Maximizing Power Efficiency with Asymmetric Multicore Systems

Amdahl's Law in the Multicore Era

Farewell to Grace Hopper—end of an era!

Extending Amdahl's law in the multicore era

Multicore CPUs for the Masses

Programming multicore computers

Power challenges may end the multicore era

Similar Documents

Dark silicon and the end of multicore scaling

Power Limitations and Dark Silicon Challenge the Future of Multicore

Maximizing power efficiency with asymmetric multicore systems

Maximizing Power Efficiency with Asymmetric Multicore Systems

Amdahl's Law in the Multicore Era

Farewell to Grace Hopper—end of an era!

Extending Amdahl's law in the multicore era

Multicore CPUs for the Masses

Programming multicore computers

Power challenges may end the multicore era