NDLI: Efficient sorting using registers and caches

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Efficient sorting using registers and caches

Content Provider	ACM Digital Library
Author	Wickremesinghe, Rajiv Arge, Lars Chase, Jeffrey S. Vitter, Jeffrey Scott
Copyright Year	2002
Abstract	Modern computer systems have increasingly complex memory systems. Common machine models for algorithm analysis do not reflect many of the features of these systems, e.g., large register sets, lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior. Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm behavior on real machines.A key step toward developing better models is to quantify the performance effects of features not reflected in the models. This paper explores the effect of memory system features on sorting performance. We introduce a new cache-conscious sorting algorithm, R-MERGE, which achieves better performance in practice over algorithms that are superior in the theoretical models. R-MERGE is designed to minimize memory stall cycles rather than cache misses by considering features common to many system designs.
Starting Page	9
File Format	PDF
ISSN	10846654
e-ISSN	10846654
DOI	10.1145/944618.944627
Journal	Journal of Experimental Algorithmics (JEA)
Volume Number	7
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-12-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science

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