NDLI: Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores

Content Provider	ACM Digital Library
Author	Bai, Ke Shrivastava, Aviral Lu, Jing
Copyright Year	2015
Abstract	Scaling the memory hierarchy is a major challenge when we scale the number of cores in a multicore processor. Software Managed Multicore (SMM) architectures come up as one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory [Banakar et al. 2002]. As the local memory usually is small, large applications cannot be directly executed on it. Code and data of the task mapped to each core need to be managed between global memory and local memory. This article solves the problem of efficiently managing code on an SMM architecture. The primary requirement of generating efficient code assignments is a correct management cost model. In this article, we address this problem by proposing a cost calculation graph. In addition, we develop two heuristics $\textit{CMSM}$ (Code Mapping for Software Managed multicores) and $\textit{CMSM_advanced}$ that result in efficient code management execution on the local scratchpad memory. Experimental results collected after executing applications from the MiBench suite [Guthaus et al. 2001] demonstrate that merely by adopting the correct management cost calculation, even using previous code assignment schemes, we can improve performance by an average of 12%. Combining the correct management cost model and a more optimized code mapping algorithm together, our heuristics can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks, compared to the state-of-the-art code assignment approach [Jung et al. 2010]. When compared with Instruction-level Parallelism (ILP) results, $\textit{CMSM_advanced}$ performs an average of 5% worse. We also simulate the benchmarks on a cache-based system, and find that the code management overhead on SMM core with our code management is much less than memory latency of a cache-based system.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/2738039
Volume Number	14
Issue Number	4
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-12-08
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Code Embedded systems Instruction Local memory Multicore processor Scratchpad memory
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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