NDLI: Parallelizing load/stores on dual-bank memory embedded processors

Please wait, while we are loading the content...

Parallelizing load/stores on dual-bank memory embedded processors

Content Provider	ACM Digital Library
Author	Zhuang, Xiaotong Pande, Santosh
Copyright Year	2006
Abstract	Many modern embedded processors such as DSPs support partitioned memory banks (also called X--Y memory or dual-bank memory) along with parallel load/store instructions to achieve higher code density and performance. In order to effectively utilize the parallel load/store instructions, the compiler must partition the memory-resident values and assign them to X or Y bank. This paper gives a postregister allocation solution to merge the generated load/store instructions into their parallel counterparts. Simultaneously, our framework performs allocation of values to X or Y memory banks. We first remove as many load/stores and register--register moves as possible through an excellent iterated coalescing based register allocator by Appel and George [1996]. We then attempt to parallelize the generated load/stores using a multipass approach. The basic phase of our approach attempts the merger of load/stores without duplication and web splitting. We model this problem as a graph-coloring problem in which each value is colored as either X or Y. We then construct a motion scheduling graph (MSG), based on the range of motion for each load/store instruction. MSG reflects potential instructions that could be merged. We propose a notion of pseudofixed boundaries so that the load/store movement is less affected by register dependencies. We prove that the coloring problem for MSG is NP-complete and solve it with two different heuristic algorithms with different complexity. We then propose a two-level iterative process to attempt instruction duplication, variable duplication, web splitting, and local conflict elimination to effectively merge the remaining load/stores. Finally, we clean up some multiple-aliased load/stores. To improve the performance, we combine profiling information with each stage coupled with some modifications to the algorithm. We show that our framework results in parallelization of a large number of load/stores without much growth in data and code segments. The average speedup for our optimization pass reaches roughly 13% if no profile information is available and 17% with profile information. The average code and data segment growth is controlled within 13%.
Starting Page	613
Ending Page	657
Page Count	45
File Format	PDF
ISSN	15399087
e-ISSN	15583465
DOI	10.1145/1165780.1165784
Volume Number	5
Issue Number	3
Journal	ACM Transactions on Embedded Computing Systems (TECS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-08-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	DSP architectures Memory bank allocation Parallel load/stores Profile driven optimization
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A framework for parallelizing load/stores on embedded processors (2002)

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors

Load Unbalancing Strategy for Multicore Embedded Processors

Floating-point processors join forces in parallel processing architectures

Communication-free data allocation techniques for parallelizing compilers on multicomputers

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Software Transactional Memory for GPU Architectures

Influence of compiler optimizations on system power

A Framework for Parallelizing Load/Stores on Embedded Processors

Parallelizing load/stores on dual-bank memory embedded processors

Similar Documents

A framework for parallelizing load/stores on embedded processors (2002)

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors

Load Unbalancing Strategy for Multicore Embedded Processors

Floating-point processors join forces in parallel processing architectures

Communication-free data allocation techniques for parallelizing compilers on multicomputers

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Software Transactional Memory for GPU Architectures

Influence of compiler optimizations on system power

A Framework for Parallelizing Load/Stores on Embedded Processors

Parallelizing load/stores on dual-bank memory embedded processors