NDLI: A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

Issue 4, December 2012

Issue 3, October 2012

Introduction to the Special Issue on ReCoSoC 2011

Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance

Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities

Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization

Remote FPGA Lab for Enhancing Learning of Digital Systems

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

Content Provider	ACM Digital Library
Author	Legat, Jean-Didier Lusala, Angelo Kuti
Copyright Year	2012
Abstract	This article proposes a circuit-switched router that combines Spatial Division Multiplexing (SDM) and Time Division Multiplexing (TDM) in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service (QoS) is easily guaranteed. The proposed router was synthesized on an Stratix III 3SL340F FPGA device. A 4 × 4 2D Mesh SDM-TDM Network-on-Chip (NoC) was built with the proposed router and synthesized on the 3SL340F FPGA device. The 4 × 4 2D Mesh SDM-TDM NoC was used to build on an FPGA device, a Multiprocessor System-on-Chip (MPSoC) platform consisted of 16 Nios II/f processors, 16 20-KB On-chip Memories, and 16 Network Interfaces. Synthesis results of the MPSoC platform show that the proposed router architecture can be used to built large practicable MPSoC platforms with the proposed NoC architecture with a reasonable hardware overhead and appreciable clock frequency. Simulation results show that combining SDM and TDM techniques in a router allows the highest probability of establishing paths through the network.
Starting Page	1
Ending Page	22
Page Count	22
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/2362374.2362379
Volume Number	5
Issue Number	3
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-10-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Interconnection architectures MPSoC Network-on-Chip “NoC” SDM TDM Circuit-switching Network interface Packet-switching Router
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks

A hybrid packet-circuit switched on-chip network based on SDM

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors

A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications

A hybrid packet-circuit switched on-chip network based on SDM

Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

A High-Throughput Distributed Shared-Buffer NoC Router

A low-cost and latency bypass channel-based on-chip network

Packet-switched on-chip interconnection network for system-on-chip applications

A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

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