NDLI: WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

Issue 4, September 2009

Issue 3, September 2009

Issue 2, June 2009

GUEST EDITORS’ INTRODUCTION ICFPT 2007

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA

Hardware Decompression Techniques for FPGA-Based Embedded Systems

Self-Measurement of Combinatorial Circuit Delays in FPGAs

Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits

Vector Processing as a Soft Processor Accelerator

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs

Issue 1, March 2009

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging

Content Provider	ACM Digital Library
Author	Chung, Kevin Jang, Stephen Chan, Billy Mishchenko, Alan
Copyright Year	2009
Abstract	This article presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/1534916.1534924
Volume Number	2
Issue Number	2
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA Area flow Cut enumeration Edge flow Technology mapping
Content Type	Text
Resource Type	Article
Subject	Computer Science

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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WireMap: FPGA technology mapping for improved routability

Wiremap: fpga technology mapping for improved routability and enhanced lut merging (2009).

ABSTRACT WireMap: FPGA Technology Mapping for Improved Routability

WireMap: FPGA technology mapping for improved routability (2008)

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Improvements to Technology Mapping for LUT-based FPGAs (2007)

WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging

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