NDLI: Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Please wait, while we are loading the content...

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Issue 4, January 2009

Issue 3, September 2008

On the trade-off between power and flexibility of FPGA clock networks

An open-source HyperTransport core

Particle graphics on reconfigurable hardware

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures

Issue 2, June 2008

Issue 1(Special edition on the 15th international symposium on FPGAs), March 2008

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Content Provider	ACM Digital Library
Author	Lemieux, Guy Grant, David
Copyright Year	2008
Abstract	CAD tool designers are always searching for more benchmark circuits to stress their software. In this article we present a heuristic method to generate benchmark circuits specially suited for incremental place-and-route tools. The method removes part of a real circuit and replaces it with an altered version of the same circuit to mimic an incremental design change. The alteration consists of two steps: $\textit{mutate}$ followed by $\textit{perturb}.$ The perturb step exactly preserves as many circuit characteristics as possible. While perturbing, reproduction of interconnect locality, a characteristic that is difficult to measure reliably or reproduce exactly, is controlled using a new technique, ancestor depth control (ADC). Perturbing with ADC produces circuits with postrouting properties that match the best techniques known to-date. The mutate step produces targetted mutations resulting in controlled changes to specific circuit properties (while keeping other properties constant). We demonstrate one targetted mutation heuristic, scale, to significantly change circuit size with little change to other circuit characteristics. The method is simple enough for inclusion in a CAD tool directly, and fast enough for use in on-the-fly benchmark generation.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/1391732.1391736
Volume Number	1
Issue Number	3
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-09-19
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Automated development tools Design automation Graph algorithms Hardware-supporting software Place and route Testing
Content Type	Text
Resource Type	Article
Subject	Computer Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools (2006)

Perturb+Mutate: Semi-Synthetic Circuit Generation (2008)

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

On the over-specification problem in sequential ATPG algorithms

An automated design tool for analog layouts

Placement constraints in floorplan design

Perturber: Semi-Synthetic circuit generation using ancestor control for testing incremental place and route

Automated design management using traces

RBI: Simultaneous Placement and Routing Optimization Technique

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing

Similar Documents

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools (2006)

Perturb+Mutate: Semi-Synthetic Circuit Generation (2008)

Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools

On the over-specification problem in sequential ATPG algorithms

An automated design tool for analog layouts

Placement constraints in floorplan design

Perturber: Semi-Synthetic circuit generation using ancestor control for testing incremental place and route

Automated design management using traces

RBI: Simultaneous Placement and Routing Optimization Technique

Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing