NDLI: Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 10

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 9

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 8

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 7

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 6

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 5

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 4

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 3

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 2

ACM Transactions on Reconfigurable Technology and Systems (TRETS) : Volume 1

Issue 4, January 2009

Issue 3, September 2008

Issue 2, June 2008

Issue 1(Special edition on the 15th international symposium on FPGAs), March 2008

Introduction

Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs

A Desktop Computer with a Reconfigurable Pentium®

Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

Content Provider	ACM Digital Library
Author	Matsumoto, Yohei Nakagawa, Tadashi Hioki, Masakazu Kawanami, Takashi Sekigawa, Toshihiro Koike, Hanpei Tsutsumi, Toshiyuki
Copyright Year	2008
Abstract	A new method for improving the timing yield offield-programmable gate array (FPGA) devices affected by intrinsicwithin-die variation is proposed. The timing variation is reducedby selecting an appropriate configuration for each chip from a setof independent configurations, the critical paths of which do notshare the same circuit resources on the FPGA. In this article, theactual method used to generate independent multiple configurationsby simply repeating the routing phase is shown, along with theresults of Monte Carlo simulation with 10,000 samples. Onesimulation result showed that the standard deviations of maximumcritical path delays are reduced by 28% and 49% for 10% and $30%V_{th}$ variations (σ/ μ), respectively,with 10 independent configurations. Therefore, the proposed methodis especially effective for larger $V_{th}$ variation and isexpected to be useful for suppressing the performance variation ofFPGAs due to the future increase of parameter variation. Anothersimulation result showed that the effectiveness of the proposedtechnique was saturated at the use of 10 or more configurationsbecause of the degradation of the quality of the configurations.Therefore, the use of 10 or fewer configurations is reasonable.
Starting Page	1
Ending Page	31
Page Count	31
File Format	PDF
ISSN	19367406
e-ISSN	19367414
DOI	10.1145/1331897.1331899
Volume Number	1
Issue Number	1
Journal	ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-03-17
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	FPGA Configuration Timing yield Within-die variation
Content Type	Text
Resource Type	Article
Subject	Computer Science

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Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Reduction of process variation effect on FPGAs using multiple configurations

Self-Measurement of Combinatorial Circuit Delays in FPGAs

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Statistical timing and power optimization of architecture and device for fpgas.

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

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Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

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Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

Reduction of process variation effect on FPGAs using multiple configurations

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Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations