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  1. Transactions on Architecture and Code Optimization (TACO)
  2. ACM Transactions on Architecture and Code Optimization (TACO) : Volume 13
  3. Issue 3, September 2016
  4. Variable Liberalization
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ACM Transactions on Architecture and Code Optimization (TACO) : Volume 13
Issue 4, December 2016
Issue 3, September 2016
Variable Liberalization
RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory
Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C
Optimization Models for Three On-Chip Network Problems
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache
Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures
Maximizing Heterogeneous Processor Performance Under Power Constraints
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation
List of Distinguished Reviewers ACM TACO 2014
Issue 2, June 2016
Issue 1, April 2016
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 12
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 11
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 10
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 9
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 8
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 7
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 6
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 5
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 4
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 3
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 2
ACM Transactions on Architecture and Code Optimization (TACO) : Volume 1

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Variable Liberalization

Content Provider ACM Digital Library
Author Mehta, Sanyam Yew, Pen-Chung
Copyright Year 2016
Abstract In the wake of the current trend of increasing the number of cores on a chip, compiler optimizations for improving the memory performance have assumed increased importance. Loop fusion is one such key optimization that can alleviate $\textit{memory}$ and bandwidth wall and thus improve parallel performance. However, we find that loop fusion in interesting memory-intensive applications is prevented by the existence of dependences between temporary variables that appear in different loop nests. Furthermore, known techniques of allowing useful transformations in the presence of temporary variables, such as privatization and expansion, prove insufficient in such cases. In this work, we introduce variable liberalization, a technique that selectively removes dependences on temporary variables in different loop nests to achieve loop fusion while preserving the semantical correctness of the optimized program. This removal of extra-stringent dependences effectively amounts to variable expansion, thus achieving the benefit of an increased degree of freedom for program transformation but without an actual expansion. Hence, there is no corresponding increase in the memory footprint incurred. We implement $\textit{liberalization}$ in the Pluto polyhedral compiler and evaluate its performance on nine hot regions in five real applications. Results demonstrate parallel performance improvement of 1.92 × over the Intel compiler, averaged over the nine hot regions, and an overall improvement of as much as 2.17 × for an entire application, on an eight-core Intel Xeon processor.
Starting Page 1
Ending Page 25
Page Count 25
File Format PDF
ISSN 15443566
e-ISSN 15443973
DOI 10.1145/2963101
Volume Number 13
Issue Number 3
Journal ACM Transactions on Architecture and Code Optimization (TACO)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2016-08-17
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword Polyhedral compiler Dependence refinement Liberalization Loop fusion Parallelization Scheduling
Content Type Text
Resource Type Article
Subject Hardware and Architecture Information Systems Software
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