NDLI: An accurate cost model for guiding data locality transformations

Content Provider	ACM Digital Library
Author	González, Antonio Vera, Xavier Llosa, Josep Abella, Jaume
Copyright Year	2005
Abstract	Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs exhibit sufficient data locality.The performance of the memory hierarchy can be improved by means of data and loop transformations. Tiling is a loop transformation that aims at reducing capacity misses by shortening the reuse distance. Padding is a data layout transformation targeted to reduce conflict misses.This article presents an accurate cost model that describes misses across different hierarchy levels and considers the effects of other hardware components such as branch predictors. The cost model drives the application of tiling and padding transformations. We combine the cost model with a genetic algorithm to compute the tile and pad factors that enhance the program performance.To validate our strategy, we ran experiments for a set of benchmarks on a large set of modern architectures. Our results show that this scheme is useful to optimize programs' performance. When compared to previous approaches, we observe that with a reasonable compile-time overhead, our approach gives significant performance improvements for all studied kernels on all architectures.
Starting Page	946
Ending Page	987
Page Count	42
File Format	PDF
ISSN	01640925
e-ISSN	15584593
DOI	10.1145/1086642.1086646
Volume Number	27
Issue Number	5
Journal	ACM Transactions on Programming Languages and Systems (TOPLAS)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-09-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cache memories Genetic algorithms Padding Tiling
Content Type	Text
Resource Type	Article
Subject	Software

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