NDLI: Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers

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Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers

Content Provider	ACM Digital Library
Author	Zhao, Bo Yang, Jun Zhang, Youtao Xu, Yi
Copyright Year	2015
Abstract	Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multicore processors. However, the virtual channel (VC) buffers in the NoC consume significant dynamic and leakage power. To improve the energy efficiency of the router design, it is advantageous to use small buffer sizes while still maintaining throughput of the network. This article proposes two new virtual channel allocation (VA) mechanisms, termed fixed VC assignment with dynamic VC allocation (FVADA) and adjustable VC assignment with dynamic VC allocation (AVADA). VCs are designated to output ports and allocated to packets according to such assignment. This can help to reduce the head-of-line blocking. Such VC-output port assignment can also be adjusted dynamically to accommodate traffic changes. Simulation results show that both mechanisms can improve network throughput by 41% on average. Real traffic evaluation shows a network latency reduction of up to 66%. In addition, AVADA can outperform the baseline in throughput with only half of the buffer size. Finally, we are able to achieve comparable or better throughput than a previous dynamic VC allocator while reducing its critical path delay by 57%. Hence, the proposed VA mechanisms are suitable for low-power, high-throughput, and high-frequency NoC designs.
Starting Page	1
Ending Page	23
Page Count	23
File Format	PDF
ISSN	23294949
e-ISSN	23294957
DOI	10.1145/2742349
Volume Number	2
Issue Number	1
Journal	ACM Transactions on Parallel Computing (TOPC)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-05-21
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Chip multiprocessor Dynamic allocation Network-on-chip Thousand-core Virtual channel Virtual channel allocation
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Modeling and Simulation Computer Science Applications Software Computational Theory and Mathematics

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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