NDLI: Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy

Content Provider	ACM Digital Library
Author	Yeh, Chang-Ching Yeh, Chingwei Chang, Kuei-Chung Chen, Tien-Fu
Copyright Year	2011
Abstract	Power gating is an effective technique for reducing leakage power in deep submicron CMOS technology. Microarchitectural techniques for power gating of functional units have been developed by detecting suitable idle regions and turning them off to reduce leakage energy consumption; however, wakeup of functional units is needed when instructions are ready for execution such that wakeup overhead is naturally incurred. This study presents time-based power gating with reference pre-wakeup (PGRP), a novel predictive strategy that detects suitable idle periods for power gating and then enables pre-wakeup of needed functional units for avoiding wakeup overhead. The key insight is that most wakeups are repeated due to program locality. Thus, the pre-wakeup predictor learns the wakeup events and selects which prior branch instruction can provide early wakeup (wakeup patterns are visible); these information are then used to adequately prepare available functional units for instruction execution. Simulation results with benchmarks from SPEC2000 applications show that substantial leakage energy reduction with negligible performance degradation (0.38% on average) is worthwhile.
Starting Page	1
Ending Page	27
Page Count	27
File Format	PDF
ISSN	15443566
e-ISSN	15443973
DOI	10.1145/2019608.2019615
Volume Number	8
Issue Number	3
Journal	ACM Transactions on Architecture and Code Optimization (TACO)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-10-18
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Low power Leakage-power reduction Power gating
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture Information Systems Software

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