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| Content Provider | ACM Digital Library |
|---|---|
| Author | Tang, Zhizhong Gao, Guang R. Douillet, Alban Rong, Hongbo Govindarajan, R. |
| Copyright Year | 2007 |
| Abstract | Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. This paper proposes a three-step approach, called single-dimension software pipelining (SSP), to software pipeline a loop nest at an arbitrary loop level that has a rectangular iteration space and contains no sibling inner loops in it. The first step identifies the most profitable loop level for software pipelining in terms of initiation rate, data reuse potential, or any other optimization criteria. The second step simplifies the multidimensional data-dependence graph (DDG) of the selected loop level into a one-dimensional DDG and constructs a one-dimensional (1D) schedule. Based on the one-dimensional schedule, the third step derives a simple mapping function that specifies the schedule time for the operation instances in the multidimensional loop. The classical modulo scheduling is subsumed by SSP as a special case. SSP is also closely related to hyperplane scheduling, and, in fact, extends it to be resource constrained. We prove that SSP schedules are correct and at least as efficient as those schedules generated by traditional modulo scheduling methods. We extend SSP to schedule imperfect loop nests, which are most common at the instruction level. Multiple initiation intervals are naturally allowed to improve execution efficiency. Feasibility and correctness of our approach are verified by a prototype implementation in the ORC compiler for the IA-64 architecture, tested with loop nests from Livermore and SPEC2000 floating-point benchmarks. Preliminary experimental results reveal that, compared to modulo scheduling, software pipelining at an appropriate loop level results in significant performance improvement. Software pipelining is beneficial even with prior loop transformations. |
| File Format | |
| ISSN | 15443566 |
| e-ISSN | 15443973 |
| DOI | 10.1145/1216544.1216550 |
| Volume Number | 4 |
| Issue Number | 1 |
| Journal | ACM Transactions on Architecture and Code Optimization (TACO) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2007-03-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Software pipelining Loop transformation Modulo scheduling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture Information Systems Software |
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