NDLI: Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs

Content Provider	ACM Digital Library
Author	Yan, Jin-Tai
Copyright Year	2016
Abstract	Due to the inappropriate assignment of bump pads or the improper assignment of I/O buffers, the constructed buffered I/O signals in an area-I/O flip-chip design may yield longer maximum delay. In this article, the problem of assigning performance-driven buffered I/O signals in an area-I/O flip-chip design is first formulated. Furthermore, the assignment of the buffered I/O signals can be divided into two sequential phases: Construction of performance-driven I/O signals and Assignment of timing-constrained I/O buffers. Finally, an efficient matching-based approach is proposed to construct the performance-driven I/O signals for the given I/O pins and assign the timing-constrained I/O buffers into the constructed I/O signals in the assignment of the buffered I/O signals in an area-I/O flip-chip design. Compared with the experimental results of seven tested circuits in the Elmore delay model, the experimental results show that the matching-based assignment in our proposed approach can reduce 3.56% of the total path delay, 9.72% of the maximum input delay, 5.90% of the input skew, 5.64% of the maximum output delay, and 6.25% of the output skew on average by reassigning the I/O buffers. Our proposed approach can further reduce 38.89% of the total path delay, 44.00% of the maximum input delay, 49.13% of the input skew, 44.93% of the maximum output delay, and 50.82% of output skew on average by reconstructing the I/O signals and reassigning the I/O buffers into the I/O signals. Compared with the experimental results of seven tested circuits in Peng's [Peng et al. 2006] publication, the experimental results show that our proposed matching-based approach can further reduce 71.06% of the total path delay, 67.83% of the maximum input delay, 59.84% of the input skew, 68.87% of the maximum output delay, and 61.46% of the output skew on average. On the other hand, compared with the experimental results of five tested circuits in Lai's [Lai and Chen 2008] publication, the experimental results show that our proposed approach can further reduce 75.36% of the total path delay, 48.94% of the input skew, and 52.80% of the output skew on the average.
Starting Page	1
Ending Page	24
Page Count	24
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2818642
Volume Number	21
Issue Number	2
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-01-28
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Flip-chip design I/O buffer Voronoi diagram Buffered I/O signal Bump pad Minimum weight perfect matching
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

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