NDLI: Reducing Contention in Shared Last-Level Cache for Throughput Processors

Content Provider	ACM Digital Library
Author	Jou, Jing-Yang Kuo, Hsien-Kai Lai, Bo-Cheng Charles
Copyright Year	2014
Abstract	Deploying the Shared Last-Level Cache (SLLC) is an effective way to alleviate the memory bottleneck in modern throughput processors, such as GPGPUs. A commonly used scheduling policy of throughput processors is to render the maximum possible thread-level parallelism. However, this greedy policy usually causes serious cache contention on the SLLC and significantly degrades the system performance. It is therefore a critical performance factor that the thread scheduling of a throughput processor performs a careful trade-off between the thread-level parallelism and cache contention. This article characterizes and analyzes the performance impact of cache contention in the SLLC of throughput processors. Based on the analyses and findings of cache contention and its performance pitfalls, this article formally formulates the aggregate working-set-size-constrained thread scheduling problem that constrains the aggregate working-set size on concurrent threads. With a proof to be NP-hard, this article has integrated a series of algorithms to minimize the cache contention and enhance the overall system performance on GPGPUs. The simulation results on NVIDIA's Fermi architecture have shown that the proposed thread scheduling scheme achieves up to 61.6% execution time enhancement over a widely used thread clustering scheme. When compared to the state-of-the-art technique that exploits the data reuse of applications, the improvement on execution time can reach 47.4%. Notably, the execution time improvement of the proposed thread scheduling scheme is only 2.6% from an exhaustive searching scheme.
Starting Page	1
Ending Page	28
Page Count	28
File Format	PDF
ISSN	10844309
e-ISSN	15577309
DOI	10.1145/2676550
Volume Number	20
Issue Number	1
Journal	ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-11-18
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Throughput processors Cache contention Shared last-level cache Thread scheduling Thread-level parallelism
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A predictive decode filter cache for reducing power consumption in embedded processors

Addressing shared resource contention in multicore processors via scheduling (SIGP, Vol. 45, Issue. 3)

Memory management in NUMA multicore systems:trapped between cache contention and interconnect overhead

Implementing the scale vector-thread processor

Cache-Conscious Thread Scheduling for Massively Multithreaded Processors

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Survey of scheduling techniques for addressing shared resources in multicore processors

CUDA-NP:realizing nested thread-level parallelism in GPGPU applications

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

Reducing Contention in Shared Last-Level Cache for Throughput Processors

Similar Documents

A predictive decode filter cache for reducing power consumption in embedded processors

Addressing shared resource contention in multicore processors via scheduling (SIGP, Vol. 45, Issue. 3)

Memory management in NUMA multicore systems:trapped between cache contention and interconnect overhead

Implementing the scale vector-thread processor

Cache-Conscious Thread Scheduling for Massively Multithreaded Processors

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture

Survey of scheduling techniques for addressing shared resources in multicore processors

CUDA-NP:realizing nested thread-level parallelism in GPGPU applications

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

Reducing Contention in Shared Last-Level Cache for Throughput Processors