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| Content Provider | ACM Digital Library |
|---|---|
| Author | Pravadelli, Graziano Bombieri, Nicola Fummi, Franco |
| Copyright Year | 2008 |
| Abstract | In transaction-level modeling (TLM), verification methodologies based on transactions allow testbenches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking. |
| Starting Page | 1 |
| Ending Page | 22 |
| Page Count | 22 |
| File Format | |
| ISSN | 10844309 |
| e-ISSN | 15577309 |
| DOI | 10.1145/1367045.1367056 |
| Volume Number | 13 |
| Issue Number | 3 |
| Journal | ACM Transactions on Design Automation of Electronic Systems (TODAES) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2008-07-25 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Model checking TBV TLM Fault models Functional verification |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering |
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