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| Content Provider | ACM Digital Library |
|---|---|
| Author | Davoodi, Azadeh Srivastava, Ankur |
| Copyright Year | 2005 |
| Abstract | This article addresses the problem of voltage scheduling in unpredictable situations. The voltage scheduling problem assigns voltages to operations such that the power is minimized under a clock delay constraint. In the presence of unpredictabilities, meeting the clock latency constraint cannot be guaranteed. This article proposes a novel risk management based technique to solve this problem. Here, the risk management paradigm assigns a quantified value to the amount of risk the designer is willing to take on the clock cycle constraint. The algorithm then assigns voltages in order to meet the expected value of clock cycle constraint while keeping the maximum delay within the specified “risk” and minimizing the power. The proposed algorithm is based on dynamic programming and is optimal for trees. Experimental results show that the traditional voltage scheduling approach is incapable of handling unpredictabilities. Our approach is capable of generating an effective tradeoff between power and “risk”: the more the risk, the less the power. The results show that a small increase in design risk positively affects the power dissipation. |
| Starting Page | 354 |
| Ending Page | 368 |
| Page Count | 15 |
| File Format | |
| ISSN | 10844309 |
| e-ISSN | 15577309 |
| DOI | 10.1145/1059876.1059884 |
| Volume Number | 10 |
| Issue Number | 2 |
| Journal | ACM Transactions on Design Automation of Electronic Systems (TODAES) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2005-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Predictability Design closure Low power Voltage scheduling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering |
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