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| Content Provider | ACM Digital Library |
|---|---|
| Author | Parhi, Keshab K. Sundararajan, Vijay Sapatnekar, Sachin S. |
| Copyright Year | 2004 |
| Abstract | This article describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle $\textit{both}$ setup and hold constraints. Given a circuit $\textit{G}$ and a target clock period $\textit{c},$ our algorithm either outputs a retimed version of $\textit{G}$ satisfying setup and hold constraints or reports that such a solution is not possible, in $O(∣V∣^{3}log∣V∣log(∣V∣C))$ steps, where $∣\textit{V}∣$ corresponds to number of gates in the circuit and $\textit{C}$ is equal to the number of registers in the circuit. This is the first polynomial-time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues into consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that problem statement are also demonstrated in simulation for the approach presented here. Finally, a basis is provided for deriving efficient heuristics for addressing both long-path and short-path requirements by combining the techniques of retiming and min-delay padding. |
| Starting Page | 273 |
| Ending Page | 289 |
| Page Count | 17 |
| File Format | |
| ISSN | 10844309 |
| e-ISSN | 15577309 |
| DOI | 10.1145/1013948.1013949 |
| Volume Number | 9 |
| Issue Number | 3 |
| Journal | ACM Transactions on Design Automation of Electronic Systems (TODAES) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2004-07-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Minimum area retiming Application of mincost network flow Longpath circuit constraints Minimum delay padding Shortpath circuit constraints |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering |
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