NDLI: High-voltage UMOSFETs in 4H SiC

Content Provider	IEEE Xplore Digital Library
Author	Khan, I.A. Cooper Jr., J.A. Capano, M.A. Isaacs-Smith, T. Williams, J.R.
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Khan, I.A.; Cooper, J.A., Jr.; Capano, M.A.)
Abstract	We report the design and fabrication of UMOSFETs on 4H-SiC with specific on-resistances of 105.1 m/spl Omega/ cm/sup 2/ at a current density of 100 A/cm/sup 2/ and blocking voltage of 5,050 V. These devices incorporate an extended self-aligned p-bottom implant to protect the gate oxide from high electric fields. A novel shadow implant mask was developed to shield the sidewalls from any unwanted p-bottom implant. These UMOSFETs are also the first to incorporate a post-oxidation anneal (POA) in nitric oxide (NO) to improve the inversion layer electron mobility. A single zone JTE (junction termination extension) with peak blocking voltage of 7,500 V was implemented in the device design.
Sponsorship	IEEE Electron Devices Soc. Inst. Electr. Eng. Japan
Starting Page	157
Ending Page	160
File Size	453452
Page Count	4
File Format	PDF
ISBN	0780373189
DOI	10.1109/ISPSD.2002.1016195
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon carbide Implants Protection Voltage Annealing Electron mobility Numerical simulation Fabrication Current density Silicon devices
Content Type	Text
Resource Type	Article

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