NDLI: Next-generation power-aware design

Content Provider	IEEE Xplore Digital Library
Author	Sakurai, T.
Copyright Year	2007
Description	Author affiliation: Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan (Sakurai, T.)
Abstract	Summary form only given. Reducing power is still the main interest in the recent integrated circuit designs. Some of the new low-power design approaches are covered in this talk. Three-dimensional stacking of chips is an effective way to reduce power by decreasing inter-chip communication energy. A low-power yet low-cost interconnection method among stacked chips is wireless communication by L-coupling and C-coupling. The recent advances in these proximity communication approaches are discussed. The other effective approach for achieving low power is to explore operations under ultra-low supply voltage. The effect of variation in the ultra-low operating supply voltage regime is discussed with measurement results. Other point of interest for power-aware systems is the source of energy. The limited access to the power source has been a limiter for the ubiquitous electronics to fly. Wireless transmission of power will offer new application scenes for ubiquitous electronics. The talk also covers an interesting yet exotic integrated circuit made of organic transistors and MEMS switches which acts as a wireless power transmission sheet and may provide a solution to last-meter problem of energy-net.
Starting Page	383
Ending Page	384
File Size	116456
Page Count	2
File Format	PDF
ISBN	9781424486342
e-ISBN	9781605581095
DOI	10.1145/1393921.1393927
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-08-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Very large scale integration Integrated circuit interconnections Semiconductor device modeling Voltage Random access memory Web page design Electronic mail Integrated circuit synthesis Stacking Wireless communication proximity communication SiP VLSI low power low voltage organic circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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