NDLI: Power-aware operand delivery

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Power-aware operand delivery

Content Provider	IEEE Xplore Digital Library
Author	Gunadi, E. Lipasti, M.H.
Copyright Year	2007
Description	Author affiliation: Electr. & Comput. Eng. Dept., Univ. of Wisconsin, Madison, WI, USA (Gunadi, E.; Lipasti, M.H.)
Abstract	Based on operand delivery, existing microprocessors can be categorized into architected register file (ARF) or physical register file (PRF) machines, both with or without payload RAM (PL). Though many previous generation microprocessors use a PRF without PL, the trend of newer microprocessors targeting lower power environments seem to be moving towards ARF with PL. We quantitatively analyze power consumption of different machine styles: ARF with PL, ARF without PL, PRF with PL, and PRF only machine. Our result shows that PRF without PL consumes the least amount of power and is fundamentally the best approach for building power-aware out-of-order microprocessors.
Starting Page	375
Ending Page	378
File Size	129422
Page Count	4
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283862
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Microprocessors Registers Energy consumption Power engineering and energy Payloads Read-write memory Design methodology Automatic control Portable computers Physics computing renaming microarchitecture power
Content Type	Text
Resource Type	Article

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