NDLI: Exact zero skew

Please wait, while we are loading the content...

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

1992 IEEE/ACM International Conference on Computer-Aided Design

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (91CH3026-2)

A cell-replicating approach to minicut-based circuit partitioning

On clustering for minimum delay/ara

Fast spectral methods for ratio cut partitioning and clustering

iMACSIM: a program for multi-level analog circuit simulation

A modified envelope-following approach to clocked analog circuit simulation

An accelerated steady-state method for networks with internally controlled switches

Automatic synthesis of time-stationary controllers for pipelined data paths

Layout-area models for high-level synthesis

Efficient microcode arrangement and controller synthesis for application specific integrated circuits

A new performance driven placement algorithm

RITUAL: a performance driven placement algorithm for small cell ICs

Wafer packing for full mask exposure fabrication

A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping

An impulse-response based linear time-complexity algorithm for lossy interconnect simulation

Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations

Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation

Evaluating RC-interconnect using moment-matching approximations

The effects of false paths in high-level synthesis

A scheduling algorithm for conditional resource sharing

Optimizing resource utilization using transformations

An algorithm for component selection in performance optimized scheduling

Optimal module implementation and its application to transistor placement

Track assignment in the Pathway datapath layout assembler

Flexible block-multiplier generation

Transient three-dimensional mixed-level circuit and device simulation: algorithms and applications

Conjugate direction waveform methods for transient two-dimensional simulation of MOS devices

Transient sensitivity computation for waveform relaxation-based timing simulation

Heuristic minimization of multiple-valued relations

LSAT-an algorithm for the synthesis of two level threshold gate networks

Layout driven logic restructuring/decomposition

Data framework for VLSI design

SLIM: a system for ASIC library management

Estimating essential design characteristics to support project planning for ASIC design management

Rapid-prototyping of hardware and software in a unified framework

Improved methods for IC yield and quality optimization using surface integrals

New simulation methods for MOS VLSI timing and reliability

Circuit optimization driven by worst-case distances

Circuit performance variability reduction: principles, problems, and practical solutions

Delay computation in combinational logic circuits: theory and algorithms

Timing analysis and delay-fault test generation using path-recursive functions

Performance enhancement through the generalized bypass transform

Delay optimization of combinational logic circuits by clustering and partial collapsing

DIATEST: a fast diagnostic test pattern generator for combinational circuits

Knowledge-based debugging of ASICs: real case study and performance analysis

Beta: behavioral testability analysis

Path sensitization in critical path problem

FPD-an environment for exact timing analysis

A new approach to solving false path problem in timing analysis

State assignment based on the reduced dependency theory and recent experimental results

A flexible scheme for state assignment based on characteristics of the FSM

Encoding multiple outputs for improved column compaction

Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware

BISTSYN-a built-in self-test synthesizer

Comparison of random test vector generation strategies

Built-in self-test in multi-port RAMs

The Hercules CAD task management system

The configuration management for version control in an object-oriented VHDL design environment

SADE: a graphical tool for VHDL-based system analysis

System specification and synthesis with the SpecCharts language

Compiling multi-dimensional data streams into distributed DSP ASIC memory

Post-processor for data path synthesis using multiport memories

Clustering techniques for register optimization during scheduling preprocessing

Scheduling in programmable video signal processors

Circuit comparison by hierarchical pattern matching

HIVE: an efficient interconnect capacitance extractor to support submicron multilevel interconnect designs

Hierarchical analyzer for VLSI power supply networks based on a new reduction method

Automatic detection of MOS synchronizers for timing verification

Static timing analysis using interval constraints

The calculation of signal stable ranges in combinational circuits

Automatic synthesis of locally-clocked asynchronous state machines

Synthesis of hazard-free asynchronous circuits from graphical specifications

Synthesis for testability techniques for asynchronous circuits

Timing-oriented routers for PCB layout design of high-performance computers

Exact zero skew

PROTON: a parallel detailed router on an MIMD parallel machine

A parallel Steiner heuristic for wirelength estimation of large net populations

Extraction of gate level models from transistor circuits by four-valued symbolic analysis

Bipolar timing modeling including interconnects based on parametric correction

A stimulus/response system based on hierarchical timing diagrams

Obtaining functionally equivalent simulations using VHDL and a time-shift transformation

Converting combinational circuits into pipelined data paths

An ATPG-based approach to sequential logic optimization

Calculating resettability and reset sequences

Verification of relations between synchronous machines

A behavioral representation for Nyquist rate A/D converters

Automating analog circuit design using constrained optimization techniques

Techniques for simultaneous placement and routing of custom analog cells in KOAN/ANAGRAM II

A fault oriented partial scan design approach

Timing-driven partial scan

Ordering storage elements in a single scan chain

Finite state machine decomposition by transition pairing

Don't care sequences and the optimization of interacting finite state machines

An automatic finite state machine synthesis using temporal logic decomposition

Algorithms for three-layer over-the-cell channel routing

A new model for over-the-cell channel routing with three layers

A channel router for single layer customization technology

A hierarchical methodology to improve channel routing by pin permutation

A new test generation method for sequential circuits

Test generation for synchronous sequential circuits based on fault extraction

Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy

A signal-driven discrete relaxation technique for architectural level test generation

Extended BDD's: trading off canonicity for structure in verification algorithms

Probabilistic design verification

Minimization of binary decision diagrams based on exchanges of variables

Variable ordering and selection of FSM traversal

A convex optimization approach to transistor sizing for CMOS circuits

A new linear placement algorithm for cell generation

Two-dimensional layout synthesis for large-scale CMOS circuits

A systematic approach for designing testable VLSI circuits

Design for easily applying test vectors to improve delay fault coverage

The impedance fault model and design for robust impedance fault testability

Application of Boolean unification to combinational logic synthesis

Extracting local don't cares for network optimization

Observability relations and observability don't cares

Minimizing channel density by shifting blocks and terminals

The crossing distribution problem

On topological via minimization and routing

Switchbox Steiner tree problem in presence of obstacles

PARIS: a parallel pattern fault simulator for synchronous sequential circuits

Methods for reducing events in sequential circuit fault simulation

Fault simulation for multiple faults using shared BDD representation of fault sets

A switch-level matrix approach to transistor-level fault simulation

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Improved logic synthesis algorithms for table look up architectures

Technology mapping of lookup table-based FPGAs for performance

Performance directed synthesis for table look up programmable gate arrays

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in