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Semiconductor Device Having A Porous Low-k Structure
| Content Provider | The Lens |
|---|---|
| Abstract | The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens. |
| Related Links | https://www.lens.org/lens/patent/106-294-606-324-30X/frontpage |
| Language | English |
| Publisher Date | 2017-02-02 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2015-07-30 |
| Applicant | Taiwan Semiconductor Mfg Co Ltd |
| Application No. | 201514813177 |
| Claim | A semiconductor device, comprising: a substrate; a plurality of conductive elements disposed over the substrate, wherein the conductive elements are separated from one another by a plurality of openings; and a dielectric material disposed over and between the conductive elements, wherein the dielectric material includes: a first portion that is disposed inside the openings; and a second portion that is disposed over the openings and over the conductive elements; wherein the first portion is substantially more porous than the second portion. The semiconductor device of claim 1 , wherein the first portion of the dielectric material has a substantially lower dielectric constant than the second portion of the dielectric materia The semiconductor device of claim 1 , wherein: the dielectric material contains a plurality of porous structures; and the porous structures disposed in the first portion of the dielectric material are substantially larger in size than the porous structures disposed in the second portion of the dielectric materia The semiconductor device of claim 1 , further comprising a barrier layer disposed between the conductive elements and the dielectric material, wherein surfaces of the barrier layer have hydrophilic characteristics. The semiconductor device of claim 1 , wherein the conductive elements are metal lines of an interconnect structure. The semiconductor device of claim 1 , further comprising one or more conductive vias disposed over at least some of the conductive elements. The semiconductor device of claim 1 , wherein the dielectric material has a dielectric constant less than a dielectric constant of silicon dioxide. A semiconductor device, comprising: a substrate; a plurality of metal elements disposed over the substrate; and a low-k dielectric material disposed in between, and over, the metal elements, wherein the low-k dielectric material includes: a first portion that is disposed between the metal elements, the first portion having a first dielectric constant; and a second portion that is disposed over the metal elements, the second portion having a second dielectric constant, wherein the first portion is more porous than the second portion; wherein: the first dielectric constant is lower than the second dielectric constant; and the first dielectric constant and the second dielectric constant are each less than a dielectric constant of silicon dioxide. (canceled) The semiconductor device of claim 8 , wherein: the first portion has a first porosity in a range from about 10%-15%; and the second portion has a second porosity in a range from about 20%-30%. The semiconductor device of claim 8 , further comprising a barrier layer disposed between the metal elements and the low-k dielectric material, wherein surfaces of the barrier layer are hydrophilic. The semiconductor device of claim 8 , wherein the metal elements are metal lines of an interconnect structure, and wherein the interconnect structure further comprises one or more vias disposed over at least some of the metal elements. 13 - 20 . (canceled) A semiconductor device, comprising: a substrate; a plurality of conductive elements over the substrate, wherein the conductive elements are separated from one another by a plurality of openings; a hydrophilic barrier layer over the conductive elements, wherein the barrier layer covers sidewalls of the openings; and a porous dielectric material over the barrier layer and inside the openings. The semiconductor device of claim 21 , wherein the porous dielectric material includes: a first portion that is disposed between the conductive elements, the first portion having a first dielectric constant; and a second portion that is disposed over the conductive elements, the second portion having a second dielectric constant. The semiconductor device of claim 22 , wherein: the first dielectric constant is lower than the second dielectric constant; and the first dielectric constant and the second dielectric constant are each less than a dielectric constant of silicon dioxide. The semiconductor device of claim 21 , further comprising: a via opening over at least one of the conductive elements; and a conductive material in the via opening. The semiconductor device of claim 21 , wherein the porous dielectric material comprises configuring a mixing ratio of a methyl-containing precursor component to a methyl-free precursor component. The semiconductor device of claim 21 , wherein the porous dielectric material includes porogens congregated inside the openings. The semiconductor device of claim 21 , wherein the porous dielectric material has a dielectric constant lower than a dielectric constant of silicon dioxide. The semiconductor device of claim 21 , wherein the hydrophilic barrier layer completely covers sidewalls of the openings. The semiconductor device of claim 1 , wherein: the first portion has a first porosity in a range from about 10%-15%; and the second portion has a second porosity in a range from about 20%-30%. |
| CPC Classification | Semiconductor Devices Not Covered By Class H10 |
| Extended Family | 188-422-366-055-267 078-172-089-236-627 148-554-509-205-749 137-430-361-602-030 032-708-721-208-974 106-294-606-324-30X 002-358-975-538-820 183-470-588-480-685 006-213-354-952-322 000-290-995-946-732 067-549-830-024-079 171-535-821-284-429 120-200-567-839-892 098-785-977-537-61X |
| Patent ID | 20170033043 |
| Inventor/Author | Lin Bo-jiun Chen Hai-ching Bao Tien-i |
| IPC | H01L23/522 H01L21/02 H01L21/768 H01L23/528 |
| Status | Active |
| Owner | Taiwan Semiconductor Manufacturing Company Ltd |
| Simple Family | 188-422-366-055-267 078-172-089-236-627 148-554-509-205-749 137-430-361-602-030 032-708-721-208-974 106-294-606-324-30X 002-358-975-538-820 183-470-588-480-685 006-213-354-952-322 000-290-995-946-732 067-549-830-024-079 171-535-821-284-429 120-200-567-839-892 098-785-977-537-61X |
| CPC (with Group) | H01L21/02203 H01L21/762 H01L23/53223 H01L23/53238 H01L23/53266 H01L23/5329 H01L21/76885 H01L21/7682 H01L21/76826 H01L21/76834 H01L2221/1047 H01L21/764 H01L23/5226 H01L23/528 H01L21/02362 H10D62/115 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent Application Publication |
