Semiconductor Package Structure Having A Heat Dissipation Structure

Content Provider	The Lens
Abstract	A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.
Related Links	https://www.lens.org/lens/patent/012-298-407-767-431/frontpage
Language	English
Publisher Date	2019-05-30
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2017-11-28
Applicant	Advanced Semiconductor Eng
Application No.	201715824913
Claim	A semiconductor substrate, comprising: a dielectric layer having a surface; a heat dissipation structure surrounded by the dielectric layer, the heat dissipation structure defining a space and including a liquid in the space; and a first patterned conductive layer disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure. The semiconductor substrate of claim 1 , wherein a boiling point of the liquid is no greater than 100° C. The semiconductor substrate of claim 2 , wherein the liquid includes at least one of water, an alcohol, a ketone or ammonia. The semiconductor substrate of claim 3 , wherein a pressure within the space is lower than 1 atm. The semiconductor substrate of claim 4 , wherein a surface within the space of the heat dissipation structure includes a capillary structure, a porous surface, a non-planar surface, or a rough surface. The semiconductor substrate of claim 1 , wherein the first patterned conductive layer and a portion of the heat dissipation structure are integrally formed as a monolithic structure. The semiconductor substrate of claim 1 , wherein the heat dissipation structure includes a heat absorbing end and a cooling end opposite to the heat absorbing end. The semiconductor substrate of claim 7 , further comprising a second patterned conductive layer including a via, wherein the second patterned conductive layer is thermally connected with the cooling end of the heat dissipation structure through the via of the second patterned conductive layer. The semiconductor substrate of claim 8 , further comprising a third patterned conductive layer including a via, wherein the third patterned conductive layer is thermally connected with the heat absorbing end of the heat dissipation structure through the via of the third patterned conductive layer. The semiconductor substrate of claim 1 , wherein the heat dissipation structure includes an upper portion, a lower portion and an adhesive layer disposed between the upper portion and the lower portion. The semiconductor substrate of claim 10 , wherein the heat dissipation structure includes a heat absorbing end and a cooling end opposite to the heat absorbing end, a surface of the lower portion within the space of the heat dissipation structure is a non-planar surface defining a plurality of first trenches, and the first trenches extend between the heat absorbing end and the cooling end. The semiconductor substrate of claim 11 , wherein a surface of the upper portion within the space of the heat dissipation structure defines a plurality of second trenches extending between the heat absorbing end and the cooling end. The semiconductor substrate of claim 11 , wherein the heat dissipation structure further includes a plurality of objects, wherein the objects are selected from copper (Cu) mesh, Cu fiber, sintered metal powder, or combinations of two or more thereof. The semiconductor substrate of claim 1 , wherein the heat dissipation structure further includes a plurality of objects, wherein the objects are selected from Cu mesh, Cu fiber, sintered metal powder, or combinations of two or more thereof. A semiconductor package structure, comprising: a first substrate, comprising: a dielectric layer having a surface; a heat dissipation structure surrounded by the dielectric layer, the heat dissipation structure defining a space and including a liquid in the space; and a first patterned conductive layer disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure; and a chip disposed on the first substrate and electrically and thermally connected to the first patterned conductive layer. The semiconductor package structure of claim 15 , wherein the chip includes an active layer facing the first substrate. The semiconductor package structure of claim 16 , wherein the first substrate further includes a second patterned conductive layer including a via, the heat dissipation structure includes a heat absorbing end and a cooling end opposite to the heat absorbing end, and the second patterned conductive layer is thermally connected with the cooling end of the heat dissipation structure through the via of the second patterned conductive layer. The semiconductor package structure of claim 17 , wherein the first substrate further includes a third patterned conductive layer including a via, and the third patterned conductive layer is thermally connected with the heat absorbing end of the heat dissipation structure through the via of the third patterned conductive layer. The semiconductor package structure of claim 18 , wherein the chip includes a first conductive connect, and the chip is electrically and thermally connected to the third patterned conductive layer through the first conductive connect. The semiconductor package structure of claim 19 , further comprising a pad and a second conductive connect disposed on the pad connected to the second patterned conductive layer. The semiconductor package structure of claim 15 , further comprising a second substrate disposed on the first substrate and electrically connected to the first substrate. The semiconductor package structure of claim 21 , further comprising an encapsulating material disposed between the first substrate, the chip and the second substrate. The semiconductor package structure of claim 15 , wherein the heat dissipation structure includes a heat absorbing end and a cooling end opposite to the heat absorbing end, a surface within the space of the heat dissipation structure is a non-planar surface defining a plurality of trenches, and the trenches extend between the heat absorbing end and the cooling end. 24 - 34 . (canceled)
CPC Classification	Semiconductor Devices Not Covered By Class H10
Extended Family	179-449-439-756-771 012-298-407-767-431 027-235-493-759-193 005-143-180-588-251
Patent ID	20190164871
Inventor/Author	Lee Chih Cheng Shih Yu-lin
IPC	H01L23/495 H01L21/56 H01L23/367 H01L23/42 H01L23/498
Status	Active
Owner	Advanced Semiconductor Engineering Inc
Simple Family	179-449-439-756-771 012-298-407-767-431 027-235-493-759-193 005-143-180-588-251
CPC (with Group)	H01L23/3677 H01L21/6835 H01L23/145 H01L23/427 H01L23/49822 H01L24/13 H01L24/16 H01L2221/68345 H01L2221/68354 H01L2224/13101 H01L2224/16225 H01L2924/15311 H01L2924/181 H01L23/49568 H01L21/568 H01L23/42 H01L23/49838 H01L2224/16227
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent Application Publication