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Methods of Operating A Memory Device
| Content Provider | The Lens |
|---|---|
| Abstract | A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween. |
| Related Links | https://www.lens.org/lens/patent/012-273-404-714-376/frontpage |
| Language | English |
| Publisher Date | 2019-09-24 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2018-07-05 |
| Agent | Traskbritt |
| Applicant | Micron Technology Inc |
| Application No. | 201816027598 |
| Claim | A method of operating a memory device, the method comprising: transmitting a current between a first active region and a second active region through a channel extending around a portion of a gate structure; and electrically isolating the first active region from the second active region around another portion of the gate structure with a sealed void located above the gate structure, wherein the sealed void is at least partially defined by a capping material located vertically over the gate structure and extending from the first active region to the second active region, the capping material sealing a space between the gate structure and the capping materia The method of claim 1 , wherein electrically isolating the first active region from the second active region comprises the sealed void being at least partially defined by a liner and a horizontal portion of the capping material extending between opposing portions of the liner, each of the liner and the horizontal portion of the capping material comprising an oxide. The method of claim 1 , wherein transmitting the current between the first active region and the second active region comprises transmitting the current between the first active region comprising one of an n-type dopant or a p-type dopant and the second active region comprising the other of the n-type dopant or the p-type dopant. The method of claim 1 , wherein transmitting the current comprises applying the current to a multi-layer gate structure including a first portion and a second portion embedded in the first portion. The method of claim 1 , wherein electrically isolating the first active region from the second active region comprises reducing electrical potential coupling between upper portions of each of the first active region and the second active region with the sealed void. The method of claim 5 , wherein reducing the electrical potential coupling between the upper portions of each of the first active region and the second active region comprises the sealed void comprising a gaseous material having a dielectric constant of about 1. The method of claim 5 , wherein reducing the electrical potential coupling between the upper portions of each of the first active region and the second active region comprises the sealed void being a vacuum. A method of operating a memory device, the method comprising: applying a bias to a gate structure of a memory cell; extending a channel around a portion of the gate structure; and conducting a current between a first active region and a second active region through the channel, wherein conducting the current between the first active region and the second active region comprises electrically isolating the first active region from the second active region with a sealed void located above the gate structure, the sealed void at least partially defined by a capping material located vertically over the gate structure and extending from the first active region to the second active region to seal a space between the gate structure and the capping materia The method of claim 8 , wherein conducting the current between the first active region and the second active region through the channel comprises separating the channel from the gate structure with a dielectric material located between the gate structure and each of the first active region and the second active region. The method of claim 8 , wherein electrically isolating the first active region from the second active region comprises reducing electrical potential coupling between upper portions of each of the first active region and the second active region with the sealed void being located laterally therebetween. The method of claim 8 , wherein extending the channel around the portion of the gate structure comprises extending the channel in a substrate surrounding at least a portion of the gate structure, the gate structure being recessed within the substrate. The method of claim 8 , further comprising providing electrical isolation between two adjacent memory cells of the memory device with shallow trench isolation structures comprising a dielectric material located adjacent the second active region. The method of claim 8 , wherein conducting the current between the first active region and the second active region through the channel comprises conducting the current between a source region and a drain region of the memory device. A method of operating a dual-gate system, the method comprising: receiving at least one input with the dual-gate system; conducting a current between a central active region and two opposing active regions located laterally adjacent to the central active region; transmitting the current through two opposing channels extending around lower portions of two gate structures located between the central active region and respective opposing active regions; electrically isolating the central active region from the two opposing active regions with sealed voids located above the two gate structures, wherein each of the sealed voids is at least partially defined by a capping material located vertically over each of the two gate structures and extending from the central active region to the respective opposing active regions, the capping material sealing spaces between the two gate structures and the capping material; and producing at least one output with the dual-gate system responsive at least in part to transmitting the current through the two opposing channels. The method of claim 14 , wherein transmitting the current through the two opposing channels extending around the lower portions of the two gate structures comprises transmitting the current through a substrate, the two gate structures being located in the substrate with top portions of the two gate structures being lower than a top surface of the substrate. The method of claim 14 , wherein electrically isolating the central active region from the two opposing active regions with the sealed voids comprises reducing electrical potential coupling between the central active region and each of the two opposing active regions to enhance gate-induced drain leakage performance of the dual-gate system. The method of claim 14 , further comprising applying a voltage difference between the central active region and at least one of the two opposing active regions to induce the current flowing therebetween. The method of claim 14 , wherein transmitting the current through the two opposing channels comprises each of the two gate structures having a first portion and a second portion above the first portion. The method of claim 14 , further comprising electrically isolating the dual-gate system from adjacent dual-gate systems with isolation structures laterally adjacent each of the two opposing active regions, each of the two opposing active regions located between one of the two gate structures and a respective isolation structure. The method of claim 19 , wherein electrically isolating the dual-gate system from the adjacent dual-gate systems with the isolation structures comprises a depth of each of the isolation structures being greater than a depth of each of the two gate structures. |
| CPC Classification | ELECTRONIC MEMORY DEVICES |
| Examiner | Calvin Lee |
| Extended Family | 170-858-867-408-837 133-911-943-862-758 012-273-404-714-376 082-026-778-703-795 131-575-755-692-672 177-484-995-746-778 122-189-868-268-120 194-578-907-944-138 024-252-767-575-62X 049-430-125-315-515 106-425-920-376-041 075-575-775-049-458 |
| Patent ID | 10424583 |
| Inventor/Author | Wu Tieh-chiang |
| IPC | H01L21/336 H01L27/108 H01L27/11582 H10N97/00 |
| Status | Active |
| Simple Family | 170-858-867-408-837 133-911-943-862-758 012-273-404-714-376 049-430-125-315-515 131-575-755-692-672 177-484-995-746-778 122-189-868-268-120 194-578-907-944-138 024-252-767-575-62X 082-026-778-703-795 075-575-775-049-458 106-425-920-376-041 |
| CPC (with Group) | H10B12/37 H10B12/01 H10B12/00 H10B12/30 H10B12/34 H10B12/053 H10B43/27 H10D1/00 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent/New European patent specification (amended specification after opposition procedure) |
