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Memory Arrays
| Content Provider | The Lens |
|---|---|
| Abstract | Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions. |
| Related Links | https://www.lens.org/lens/patent/012-184-857-899-049/frontpage |
| Language | English |
| Publisher Date | 2019-06-11 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2016-12-27 |
| Agent | Wells St. John P.s. |
| Applicant | Micron Technology Inc |
| Application No. | 201615391719 |
| Claim | A memory array, comprising: memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°; wordline trunk regions extending across the array and along a third direction substantially orthogonal to the second direction of the columns; wordline branch regions extending from the wordline trunk regions and along the first direction; semiconductor-material fins along the rows, each semiconductor-material fin having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions; each channel region being overlapped by a wordline branch region associated with the fin comprising the channel region; and digit lines extending along the columns and being electrically coupled with the second source/drain regions. The memory array of claim 1 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another wordline branch region on the second side of the fin. The memory array of claim 1 wherein the wordline trunk regions are over conductive lines and are spaced from the conductive lines by dielectric materia The memory array of claim 3 wherein the wordline trunk regions comprise a same composition as the conductive lines. The memory array of claim 3 wherein the wordline trunk regions comprise a different composition than the conductive lines. The memory array of claim 5 wherein the wordline trunk regions comprise metal, and wherein the conductive lines consist of conductively-doped semiconductor materia The memory array of claim 1 further comprising charge-storage devices electrically coupled with the first source/drain regions. A memory array, comprising: memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°; semiconductor-material fins along the rows; each semiconductor-material fin having two first pedestals and a single second pedestal between the first pedestals; first source/drain regions being within the first pedestals, and a second source/drain region being within the second pedestal; a first channel region being between one of the first pedestals and the second pedestal, and a second channel region being between the other of the first pedestals and the second pedestal; digit lines extending along the columns and being electrically coupled with the second source/drain regions; and wordline branch regions extending along the first direction, and joining with wordline trunk regions that extend along a direction other than the first direction; the wordline branch regions extending along the semiconductor-material fins, each semiconductor-material fin having the first channel region overlapped by a first wordline branch region associated with the fin, and having the second channel region overlapped by a second wordline branch region associated with the fin; the first and second wordline branch regions along each semiconductor-material fin being spaced from one another by insulative structures that extend along the second pedestals of the semiconductor-material fins. The memory array of claim 8 wherein the wordline branch regions are taller in regions adjacent the wordline trunk regions and shorter in regions along the channel regions. The memory array of claim 8 wherein the wordline branch regions comprise a same composition as the wordline trunk regions. The memory array of claim 8 wherein the wordline trunk regions are over conductive lines. The memory array of claim 11 wherein the wordline branch regions are not over said conductive lines. The memory array of claim 8 further comprising charge-storage devices electrically coupled with the first source/drain regions. The memory array of claim 13 wherein the charge-storage devices are capacitors. The memory array of claim 13 wherein the charge-storage devices are ferroelectric capacitors. The memory array of claim 8 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the first wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another first wordline branch region on the second side of the fin; and wherein the second wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another second wordline branch region on the second side of the fin. A memory array, comprising: memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°; semiconductor-material fins along the rows; each semiconductor-material fin having two first pedestals and a single second pedestal between the first pedestals; first source/drain regions being within the first pedestals, and a second source/drain region being within the second pedestal; a first channel region being between one of the first pedestals and the second pedestal, and a second channel region being between the other of the first pedestals and the second pedestal; the first source/drain region being beneath a first trough which is between said one of the first pedestals and the second pedestal, and the second source/drain region being beneath a second trough which is between said other of the first pedestals and the second pedestal; digit lines extending along the columns and being electrically coupled with the second source/drain regions; wordline trunk regions extending across the array and along a third direction substantially orthogonal to the second direction of the columns; and wordline branch regions extending from the wordline trunk regions and along the first direction; the wordline branch regions extending along the semiconductor-material fins, each semiconductor-material fin having the first channel region overlapped by a first wordline branch region associated with the fin, and having the second channel region overlapped by a second wordline branch region associated with the fin and coupled with a different wordline trunk region than the first wordline branch region; the first wordline branch regions having tall regions along the wordline trunk regions and short regions extending under the first troughs, and the second wordline branch regions having tall regions along the wordline trunk regions and short regions extending under the second troughs. The memory array of claim 17 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the first wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another first wordline branch region on the second side of the fin; and wherein the second wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another second wordline branch region on the second side of the fin. The memory array of claim 17 wherein the wordline trunk regions are over conductive lines and are spaced from the conductive lines by dielectric materia The memory array of claim 19 wherein the wordline trunk regions comprise a same composition as the conductive lines. The memory array of claim 19 wherein the wordline trunk regions comprise a different composition than the conductive lines. The memory array of claim 21 wherein the wordline trunk regions comprise metal and the conductive lines consist of conductively-doped semiconductor materia The memory array of claim 19 wherein the wordline branch regions are not over the conductive lines. The memory array of claim 17 further comprising charge-storage devices electrically coupled with the first source/drain regions. |
| CPC Classification | ELECTRONIC MEMORY DEVICES STATIC STORES |
| Examiner | Farun Lu |
| Extended Family | 169-010-615-446-323 012-184-857-899-049 174-309-753-932-466 001-328-293-554-758 |
| Patent ID | 10319725 |
| Inventor/Author | Juengling Werner |
| IPC | G11C5/02 H01L27/088 H01L27/108 H01L29/78 H10N97/00 |
| Status | Active |
| Owner | Micron Technology Inc |
| Simple Family | 169-010-615-446-323 012-184-857-899-049 174-309-753-932-466 001-328-293-554-758 |
| CPC (with Group) | H10B12/36 H10B12/056 H10D1/68 H10D30/62 G11C5/025 H10B12/053 H10B12/488 H10D84/834 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent/New European patent specification (amended specification after opposition procedure) |
