Protected Trench Isolation for Fin-type Field-effect Transistors

Content Provider	The Lens
Abstract	Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.
Related Links	https://www.lens.org/lens/patent/012-033-582-029-678/frontpage
Language	English
Publisher Date	2019-06-04
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2018-03-13
Agent	Thompson Hine Llp Francois Pagette
Applicant	Globalfoundries Inc
Application No.	201815919594
Claim	A method comprising: forming a gate structure extending across a plurality of semiconductor fins; depositing a spacer layer composed of a dielectric material conformally over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins; depositing a protective layer conformally over the spacer layer; masking the protective layer over the dielectric layer in the gaps between the semiconductor fins; and after masking the protective layer over the dielectric layer in the gaps between the semiconductor fins, removing the protective layer from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer. The method of claim 1 wherein masking the protective layer over the dielectric layer in the gaps between the semiconductor fins comprises: forming a hardmask layer over the protective layer on the gate structure, the semiconductor fins, and the dielectric layer in the gaps between the semiconductor fins. The method of claim 2 wherein the hardmask layer has a planar top surface when formed, and further comprising: recessing the planar top surface of the hardmask layer relative to the gate structure and the semiconductor fins. The method of claim 3 wherein the planar top surface of the hardmask layer, after recessing, is arranged in a vertical direction between a top surface of the semiconductor fins and a top surface of the dielectric layer. The method of claim 3 wherein, after recessing, the hardmask layer has a thickness of less than or equal to 10 nanometers. The method of claim 2 wherein the hardmask layer is a spin-on hardmask. The method of claim 2 wherein the hardmask layer is a carbon-containing film. The method of claim 2 further comprising: after removing the protective layer from the gate structure and the semiconductor fins, removing the hardmask layer from the protective layer over the dielectric layer arranged in the gaps between the semiconductor fins. The method of claim 1 wherein the protective layer is composed of aluminum dioxide. The method of claim 1 wherein the protective layer is composed of a nitride of silicon or titanium oxide. The method of claim 1 wherein the protective layer is selectively removed relative to the spacer layer by a wet clean or a wet chemical etch. The method of claim 1 wherein the protective layer over the dielectric layer in the gaps between the semiconductor fins is retained after removing the protective layer from the gate structure and the semiconductor fins. The method of claim 1 wherein the dielectric layer has a top surface that is planar, each of the semiconductor fins has a first section arranged above the top surface of the dielectric layer and a second section arranged below the top surface of the dielectric layer, and the spacer layer is arranged over the first section of each of the semiconductor fins. The method of claim 1 wherein the protective layer is composed of a material that is removable selective to silicon dioxide. The method of claim 1 wherein the protective layer is deposited after the gate structure is formed. The method of claim 1 further comprising: after removing the protective layer from the gate structure and the semiconductor fins, performing a wet clean or a reactive ion etch with the protective layer over the dielectric layer in the gaps between the semiconductor fins. The method of claim 1 wherein the protective layer is deposited over the spacer layer by chemical vapor deposition or physical vapor deposition. The method of claim 1 wherein the spacer layer is arranged between the protective layer and a top surface of the dielectric layer in the gaps between the semiconductor fins. The method of claim 18 wherein the protective layer is in direct contact with the spacer layer. The method of claim 1 wherein the gate structure is cut before the protective layer is formed.
CPC Classification	Semiconductor Devices Not Covered By Class H10
Examiner	Stephen W Smoot
Extended Family	012-033-582-029-678
Patent ID	10312150
Inventor/Author	Al-amoody Fuad Liu Jinping Kassim Joseph Krishnan Bharat
IPC	H01L21/8234 H01L21/02 H01L21/033 H01L21/308 H01L21/311 H01L21/475 H01L21/762 H01L29/06 H01L29/66 H01L29/78
Status	Active
Owner	Globalfoundries U.s. Inc Globalfoundries Inc
Simple Family	012-033-582-029-678
CPC (with Group)	H01L21/76229 H10D84/0158 H10D84/038 H10D84/0151 H10D30/024 H01L21/31144 H01L21/0337 H01L21/0332 H01L21/02178 H01L21/0217 H01L21/02186 H01L21/0206 H01L21/31116 H01L21/31111 H01L21/02164 H01L21/02271 H01L21/76224 H01L21/0228 H01L21/3081 H01L21/475 H10D30/62 H10D84/0135 H10D62/115 H10D64/017 H10D84/013
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent/Patent 1st level of publication/Inventor's certificate