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Method for Fabricating An Integrated-passives Device with A Mim Capacitor and A High-accuracy Resistor on Top
| Content Provider | The Lens |
|---|---|
| Abstract | The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance. |
| Related Links | https://www.lens.org/lens/patent/012-003-559-620-585/frontpage |
| Language | English |
| Publisher Date | 2017-03-07 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2010-04-14 |
| Agent | Rajeev Madnawat |
| Applicant | Roest Aarnoud Laurens Van Leuken-peters Linda Nxp Bv |
| Application No. | 201013264816 |
| Claim | A method for fabricating an electronic component, the method comprising: fabricating, on a substrate, at least one integrated MIM capacitor having a top capacitor electrode, and a bottom capacitor electrode at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer on the top capacitor electrode, wherein the first cover layer at least partly covers the top capacitor electrode and includes a lead-containing dielectric material; thinning the first cover layer, wherein the thinning step removes a more than proportional amount of lead from the lead-containing dielectric material such that the lead-containing dielectric material has a lower concentration of lead after the thinning step than before the thinning step; fabricating an electrically insulating second cover layer on the first cover layer, wherein the second cover layer at least partly covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer on the second cover layer, wherein the resistor layer has a defined ohmic resistance. The method of claim 1 , wherein thinning the first cover layer comprises: sputtering the first cover layer back. The method of claim 1 , wherein thinning the first cover layer comprises: etching the first cover layer back. The method of claim 1 , wherein thinning the first cover layer comprises: removing between 10 and 50 nanometers of the first cover layer. The method of claim 1 , wherein the first cover layer includes lead zirconate titanate (PZT). The method of claim 1 , wherein the first cover layer has a thickness of between 30 and 300 nm after the thinning step. The method of claim 1 , wherein the resistor layer is made of at least one element from a group of Mo, Ni, Cr, Ti, Si, and W. The method of claim 1 , wherein fabricating the MIM capacitor comprises: fabricating a dielectric layer of the MIM capacitor, wherein the dielectric layer has a relative dielectric permittivity of between 100 and 5000. The method of claim 1 , wherein the second cover layer is made of silicon nitride. The method of claim 1 , further comprising: fabricating a bottom barrier layer of a dielectric material between the substrate and the bottom capacitor electrode. The method of claim 1 , further comprising: fabricating a direct connection of the resistor layer with the top capacitor electrode. The method of claim 1 , further comprising: fabricating at least one active semiconductor element on an identical substrate. The method of claim 12 , wherein the at least one active semiconductor element is an ESD protection diode. The method of claim 1 , wherein a top portion of the first cover layer has a lower concentration of lead after the thinning step than before the thinning step. The method of claim 1 , wherein the second cover layer is fabricated with a higher thickness than the first cover layer. The method of claim 1 , wherein an interconnect layer is deposited directly upon the resistor layer. The method of claim 1 , wherein the resistor layer is fabricated to form an inductor with an inductance of a desired value. The method of claim 1 , wherein the second cover layer is made of silicon oxynitride. The method of claim 1 , wherein the second cover layer is made of spin-on-glass (SOG). The method of claim 10 , wherein the bottom barrier layer includes lead zirconate titanate (PZT). |
| Examiner | Robert Huber |
| Extended Family | 001-458-390-434-817 012-003-559-620-585 118-326-399-082-166 020-867-819-625-891 |
| Patent ID | 9590027 |
| Inventor/Author | Roest Aarnoud Laurens Van Leuken-peters Linda |
| IPC | H01L21/20 H01L27/01 H01L27/02 H01L27/06 H10N97/00 |
| Status | Active |
| Owner | Nexperia B.v Nxp B.v |
| Simple Family | 001-458-390-434-817 012-003-559-620-585 118-326-399-082-166 020-867-819-625-891 |
| CPC (with Group) | H10D86/85 H10D89/601 H10D88/00 H10D1/47 H10D1/694 H10D1/682 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent/New European patent specification (amended specification after opposition procedure) |
