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Power Amplifier Circuit
| Content Provider | The Lens |
|---|---|
| Abstract | The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors. |
| Related Links | https://www.lens.org/lens/patent/011-968-000-126-855/frontpage |
| Language | English |
| Publisher Date | 2019-06-06 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2018-12-03 |
| Applicant | Qualcomm Inc |
| Application No. | 201816208398 |
| Claim | An amplifier circuit comprising: one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration, comprising: an NMOS transistor having a gate terminal electrically coupled to an input node configured to receive an input signal, a source terminal electrically coupled to ground, and a drain terminal electrically coupled to a first supply voltage through a first inductive impedance element; and a PMOS transistor having a gate terminal electrically coupled to the input node, a source terminal electrically coupled to a second supply voltage, and a drain terminal electrically coupled to ground through a second inductive impedance element, the NMOS transistor electrically coupled in parallel to the PMOS transistor; and an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration comprising one or more NMOS transistors or PMOS transistors. The amplifier circuit of claim 1 , wherein the first inductive impedance element and the second inductive impedance elements are inductively coupled. The amplifier circuit of claim 1 , wherein outputs of the NMOS transistor and the PMOS transistor are electrically coupled to provide a common output signal through one or more reactive elements. The amplifier circuit of claim 3 , wherein the one or more reactive elements comprises a first reactive element electrically coupled between the drain terminal of the NMOS transistor and an output node and a second reactive element electrically coupled between the drain terminal of the PMOS transistor and the output node. The amplifier circuit of claim 3 , wherein the one or more reactive elements comprises one or more transformers. The amplifier circuit of claim 1 , further comprising a first DC blocking capacitor electrically coupled between the input node and the gate terminal of the NMOS transistor and a second DC blocking capacitor electrically coupled between the input node and the gate terminal of the PMOS transistor. The amplifier circuit of claim 1 , wherein the NMOS transistor is a first NMOS transistor, and wherein the PMOS transistor is a first PMOS transistor, wherein the input node is a first input node configured to receive a first input signal of a differential signal and wherein each of the one or more amplifier stages further comprises: a second NMOS transistor having a gate terminal electrically coupled to a second input node configured to receive a second input signal of the differential signal, a source terminal electrically coupled to ground, and a drain terminal electrically coupled to the first supply voltage through a third inductive impedance element; and a second PMOS transistor having a gate terminal electrically coupled to the second input node configured to receive the second input signal of the differential signal, a source terminal electrically coupled to the second supply voltage, and a drain terminal electrically coupled to ground through a fourth inductive impedance element. The amplifier circuit of claim 7 , wherein the first, second, third, and fourth inductive impedance elements form a portion of one or more transformers. The amplifier circuit of claim 7 , further comprising an inter-stage matching circuit coupled between stages of the one or more amplifier stages or between the one or more amplifier stages and the output amplifier stage, the inter-stage matching circuit comprising: a transformer having a primary side electrically coupled in series on one side to the first inductive impedance element and to the third impedance inductive element on the other side; a fifth inductive impedance element electrically coupled to one side of a secondary side of the transformer and configured to provide a first output; and a sixth inductive impedance element electrically coupled to the other side of the secondary side the transformer and configured to provide a second output. The amplifier circuit of claim 9 , wherein the transformer is a tightly coupled transformer. The amplifier circuit of claim 7 , further comprising an inter-stage matching circuit coupled between stages of the one or more amplifier stages or between the one or more amplifier stages and the output amplifier stage, the inter-stage matching circuit comprising: a transformer having a primary side electrically coupled in series on one side to the drain terminal of the first PMOS transistor and electrically coupled on the other side of the primary side to the drain terminal of the second PMOS transistor, a secondary side of the transformer electrically coupled to at least one of the output amplifier stage or another stage of the one or more amplifier stages. The amplifier circuit of claim 7 , further comprising a matching circuit electrically coupled between stages of the one or more amplifier stages or between a stage of the one or more amplifier stages and the output amplifier stage, the matching circuit comprising a transformer and a capacitor electrically coupled between a ground node and a center tap of at least one of the primary or secondary sides of the transformer, the capacitor electrically coupled in series with one or more elements of the matching circuit to form a common mode short at substantially a second harmonic of an amplifier operating frequency of the amplifier circuit. The amplifier circuit of claim 7 , wherein the output amplifier stage comprises: a third NMOS transistor having a gate terminal electrically coupled to outputs of the first NMOS transistor and the first PMOS transistor of one of the one or more amplifier stages, a drain terminal electrically coupled to an output transformer, and a source terminal electrically coupled to ground; and a fourth NMOS transistor having a gate terminal electrically coupled to outputs of the second NMOS transistor and the second PMOS transistor of the one of the one or more amplifier stages, a drain terminal electrically coupled to the output transformer, and a source terminal electrically coupled to ground. The amplifier circuit of claim 1 , wherein outputs of the NMOS transistor and the PMOS transistor are coupled to provide a common output signal in at least one of the one or more amplifier stages through one or more reactive components, wherein the output amplifier stage comprises: a second NMOS transistor having a gate terminal coupled to receive the common output signal, a drain terminal electrically coupled to an amplifier output node, and a source terminal electrically coupled to ground. The amplifier circuit of claim 1 , wherein an operating frequency of the amplifier circuit is within a mmWave range. The amplifier circuit of claim 15 , wherein the amplifier circuit is one of a plurality of amplifier circuits in a phased array transceiver. An amplifier circuit comprising: a first amplifier stage comprising a first path electrically coupled to one or more input nodes and a second path electrically coupled to the one or more input nodes, the first amplifier stage comprising one or more first PMOS transistors in the first path and one or more first NMOS transistors in the second path; a second amplifier stage comprising a first path electrically coupled to the first path of the first amplifier stage and comprising one or more second NMOS transistors in the first path, the second amplifier stage comprising a second path electrically coupled to the second path of the first amplifier stage and comprising one or more second PMOS transistors in the second path; an output amplifier stage electrically coupled to the second amplifier stage and further electrically coupled to both the first path and the second path to form a common path for the output amplifier stage, the output amplifier stage comprising a non-complementary transistor configuration. The amplifier circuit of claim 17 , wherein the output amplifier stage comprises one or more NMOS transistors. The amplifier circuit of claim 17 , wherein the one or more first PMOS transistors in the first path of the first amplifier stage comprises: a first PMOS transistor having a gate terminal coupled to a first input node of the one or more input nodes, a source terminal coupled to a supply voltage, and a drain terminal electrically coupled to ground through a first inductive impedance element; a second PMOS transistor having a gate terminal coupled to a second input node of the one or more input nodes, a source terminal coupled to the supply voltage, and a drain terminal electrically coupled to ground through a second inductive impedance element. The amplifier circuit of claim 17 , wherein the one or more first NMOS transistors in the second path of the first amplifier stage comprises: a first NMOS transistor having a gate terminal coupled to a first input node of the one or more input nodes, a drain terminal coupled to a supply voltage through a first inductive impedance element, and a source terminal electrically coupled to ground; and a second NMOS transistor having a gate terminal coupled to a second input node of the one or more input nodes, a drain terminal coupled to the supply voltage through a second inductive impedance element, and a source terminal electrically coupled to ground. The amplifier circuit of claim 17 , wherein the one or more first PMOS transistors in the first path of the first amplifier stage comprises a first PMOS transistor having a gate terminal coupled to an input node of the one or more input nodes, a source terminal coupled to a first supply voltage, and a drain terminal electrically coupled to ground through a first inductive impedance element, wherein the one or more first NMOS transistors in the second path of the first amplifier stage comprises a first NMOS transistor having a gate terminal coupled to the input node, a drain terminal coupled to a second supply voltage through a second inductive impedance element, and a source terminal electrically coupled to ground, wherein the one or more second PMOS transistors in the second path of the second amplifier stage comprises a second PMOS transistor having a gate terminal coupled to a first output of the one or more first NMOS transistors in the second path of the first amplifier stage, a source terminal coupled to a third supply voltage, and a drain terminal electrically coupled to ground through a third inductive impedance element, and wherein the one or more second NMOS transistors in the first path of the second amplifier stage comprises a second NMOS transistor having a gate terminal coupled to a second output of the one or more first PMOS transistors in the first path of the first amplifier stage, a drain terminal coupled to a fourth supply voltage through a fourth inductive impedance element, and a source terminal electrically coupled to ground. The amplifier circuit of claim 17 , further comprising an inter-stage matching circuit coupled between the first amplifier stage and the second amplifier stage, the inter-stage matching circuit comprising: a first inductive impedance element electrically coupled to a first output node in the first path of the first amplifier stage; a second inductive impedance element electrically coupled to a second output node in the first path of the first amplifier stage; a transformer having a primary side electrically coupled in series on one side to the first inductive impedance element and to the second inductive impedance element on the other side; a third inductive impedance element electrically coupled to one side of a secondary side of the transformer and electrically coupled to a first input node in the first path of the second amplifier stage; and a fourth impedance inductive element electrically coupled to the other side of the secondary side of the transformer and electrically coupled to a second input node in the first path of the second amplifier stage. The amplifier circuit of claim 17 , wherein the output amplifier stage comprises: a first NMOS transistor having a gate terminal electrically coupled to the first and second paths of the second amplifier stage, a drain terminal electrically coupled to an output transformer, and a source terminal electrically coupled to ground; and a second NMOS transistor having a gate terminal coupled to the first and second paths of the second amplifier stage, a drain terminal electrically coupled to the output transformer, and a source terminal electrically coupled to ground. The amplifier circuit of claim 17 , wherein the one or more input nodes comprise a first input node and a second input node together configured to receive a differential signa The amplifier circuit of claim 17 , wherein the output amplifier stage comprises: an NMOS transistor having a gate terminal coupled to the first and second paths of the second amplifier stage, a drain terminal electrically coupled to an amplifier output, and a source terminal electrically coupled to ground. A method for amplifying a signal in an amplifier circuit, the method comprising: amplifying the signal using a first amplifier stage having a first path electrically coupled to one or more input nodes and a second path electrically coupled to the one or more input nodes, the first amplifier stage comprising one or more first PMOS transistors in the first path and one or more first NMOS transistors in the second path; amplifying the signal using a second amplifier stage having a first path electrically coupled to the first path of the first amplifier stage and comprising one or more second NMOS transistors in the first path, the second amplifier stage having a second path electrically coupled to the second path of the first amplifier stage and comprising one or more second PMOS transistors in the second path; amplifying the signal using an output amplifier stage electrically coupled to the second amplifier stage and further electrically coupled to both the first path and the second path of the second amplifier stage to form a common path for the output amplifier stage, the output amplifier stage comprising a non-complementary transistor configuration. The method of claim 26 , further comprising: determining an operating condition of the amplifier circuit; determining a bias signal magnitude of the output amplifier stage based on the operating condition; and providing the determined bias signal to the output amplifier stage. The method of claim 27 , wherein determining the operating condition includes determining a modulation scheme used for modulating data configured to be provided through the amplifier circuit, wherein determining the bias signal magnitude is based on the modulation scheme. The method of claim 28 , wherein the modulation scheme is a 64 QAM OFDM scheme. The method of claim 29 , wherein the bias signal magnitude corresponds to a gate bias voltage, wherein the gate bias voltage is increased relative to a gate bias voltage used for other modulation schemes different than the 64 QAM OFDM. |
| CPC Classification | AMPLIFIERS |
| Extended Family | 038-740-202-661-943 041-006-065-125-096 189-381-311-579-395 088-426-902-491-963 011-968-000-126-855 |
| Patent ID | 20190173439 |
| Inventor/Author | Dunworth Jeremy Park Hyunchul Ku Bon-hyun Aparin Vladimir |
| IPC | H03F3/21 H03F1/56 H03F3/195 H03F3/213 |
| Status | Active |
| Owner | Qualcomm Incorporated |
| Simple Family | 038-740-202-661-943 041-006-065-125-096 189-381-311-579-395 088-426-902-491-963 011-968-000-126-855 |
| CPC (with Group) | H03F1/0261 H03F3/193 H03F3/245 H03F3/301 H03F3/345 H03F3/45179 H03F3/45475 H03F2200/318 H03F2200/405 H03F2200/411 H03F2200/451 H03F2200/48 H03F2200/534 H03F2200/537 H03F2200/541 H03F2203/30081 H03F2203/30114 H03F2203/30144 H03F2203/45228 H03F2203/45731 H03F3/211 H03F1/565 H03F3/195 H03F3/213 H03F2200/267 H03F2200/294 H03F2200/336 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent Application Publication |
