Increased Gate Coupling Effect in Multigate Transistor

Content Provider	The Lens
Abstract	A non-volatile memory (NVM) device and a method for forming the NVM device are presented. The NVM device includes a substrate having a device region, a gate stack having a floating gate (FG) and a control gate (CG) over the device region, and source/drain (S/D) regions adjacent to the sidewalls of the gate. The FG includes a FG dielectric and a FG electrode. The CG includes a composite CG dielectric and a CG electrode. The composite CG dielectric includes a first CG dielectric and a ferroelectric second CG dielectric. The ferroelectric second CG dielectric is configured to have a negative capacitance to increase gate coupling ratio of the NVM device.
Related Links	https://www.lens.org/lens/patent/011-693-210-352-738/frontpage
Language	English
Publisher Date	2019-02-07
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2017-08-01
Applicant	Globalfoundries Sg Pte Ltd
Application No.	201715665441
Claim	A device comprising: a substrate defined with a device region; a gate stack comprising a floating gate (FG), the FG includes a FG dielectric disposed over the substrate, and a FG electrode disposed over the FG dielectric, and a control gate (CG), the CG includes a composite CG dielectric comprising a first CG dielectric disposed over the FG electrode, the first CG dielectric comprising a silicon oxide gate dielectric, and a second CG dielectric disposed over the first CG dielectric, the second CG dielectric comprises a ferroelectric second CG dielectric, and a CG electrode disposed over the ferroelectric second CG dielectric; a first source/drain (S/D) region disposed adjacent to the first sidewall of the gate stack; a second S/D region disposed adjacent to the second gate sidewall of the second gate; and wherein the ferroelectric second CG dielectric is configured to have a negative capacitance to increase gate coupling ratio. The device of claim 1 wherein the first CG dielectric comprises an oxide-nitride-oxide combo (ONO) dielectric. The device of claim 1 wherein the first CG dielectric produces a parasitic capacitance C top ; the ferroelectric second CG dielectric produces a parasitic ferroelectric capacitance C fe ; the FG dielectric produces a parasitic capacitance C bottom ; the first S/D produces a parasitic capacitance C drain ; and the second S/D produces a parasitic capacitance C source . The device of claim 3 wherein the C top , the C source , the C drain and the C bottom together form a parasitic capacitance C NVM . The device of claim 4 wherein an absolute value of the C fe of the ferroelectric second CG dielectric is larger than C NVM . The device of claim 4 wherein the ferroelectric second CG dielectric has a thickness less than a critical thickness of the ferroelectric second CG dielectric, wherein the critical thickness of the ferroelectric second CG dielectric is calculated by The device of claim 1 wherein the ferroelectric second CG dielectric comprises barium-titanium oxide (BaTiO 3 ), hafnium-zirconium oxide (HfZrO 2 ) or doped hafnium oxide (HfO 2 ). A device comprising: a substrate defined with a device region; a gate stack comprising a floating gate (FG), the FG includes a FG dielectric disposed over the substrate, and a FG electrode disposed over the FG dielectric, and a control gate (CG), the CG includes a composite CG dielectric comprising a first CG dielectric disposed over the FG electrode, and a second CG dielectric disposed over the first CG dielectric, the second CG dielectric is configured to be a negative capacitance second CG dielectric, and a CG electrode disposed over the second CG dielectric; and wherein the negative capacitance second CG dielectric is configured to produce an overall positive parasitic capacitance C NVM for the gate stack. The device of claim 8 wherein the second CG dielectric comprises a ferroelectric second CG dielectric. The device of claim 9 wherein the ferroelectric second CG dielectric comprises barium-titanium oxide (BaTiO 3 ), hafnium-zirconium oxide (HfZrO 2 ) or doped hafnium oxide (HfO 2 ). The device of claim 8 wherein the first CG dielectric comprises an oxide-nitride-oxide combo (ONO) dielectric. The device of claim 8 wherein the first CG dielectric layer produces a parasitic capacitance C top ; the second CG dielectric layer produces a parasitic capacitance C fe ; the FG dielectric produces a parasitic capacitance C bottom ; a first S/D in the substrate adjacent to a fist sidewall of the gate stack produces a parasitic capacitance C drain ; and a second S/D in the substrate adjacent to the fist sidewall of the gate stack produces a parasitic capacitance C source . The device of claim 12 wherein the C top , the C source , the C drain and the C bottom together form the parasitic capacitance C NVM . The device of claim 13 wherein an absolute value of the C fe of the second CG dielectric is larger than C NVM . The device of claim 13 wherein the second CG dielectric has a thickness less than a critical thickness of the second CG dielectric, wherein the critical thickness of the second CG dielectric is calculated by A method of forming a device comprising: providing a substrate defined with a device region; forming a gate stack on the substrate over the device region, the gate stack comprising a floating gate (FG), the FG includes a FG dielectric disposed over the substrate, and a FG electrode disposed over the FG dielectric, and a control gate (CG), the CG includes a composite CG dielectric comprising a first CG dielectric disposed over the FG electrode, and a second CG dielectric disposed over the first CG dielectric, the second CG dielectric comprises a negative capacitance second CG dielectric, and a CG electrode disposed over the second CG dielectric; forming a first source/drain (S/D) region disposed adjacent to the first sidewall of the gate stack and a second S/D region disposed adjacent to the second gate sidewall of the second gate. The method of claim 16 wherein the negative capacitance second CG dielectric comprises a ferroelectric second CG dielectric, wherein the ferroelectric second CG dielectric comprises barium-titanium oxide (BaTiO 3 ), hafnium-zirconium oxide (HfZrO 2 ) or doped hafnium oxide (HfO 2 ). The method of claim 16 wherein the first dielectric CG layer produces a parasitic capacitance C top ; the ferroelectric second CG dielectric layer produces a negative parasitic capacitance C fe ; the FG dielectric produces a parasitic capacitance C bottom ; the first S/D produces a parasitic capacitance C drain ; the second S/D produces a parasitic capacitance C source ; and wherein the C top , the C source , the C drain and the C bottom together form a parasitic capacitance C NVM . The method of claim 18 wherein an absolute value of the C fe of the second CG dielectric is about 4× larger than C NVM . The method of claim 19 wherein the second CG dielectric has a thickness less than a critical thickness of the second CG dielectric, wherein the critical thickness of the second CG dielectric is calculated by
CPC Classification	Semiconductor Devices Not Covered By Class H10
Extended Family	011-693-210-352-738
Patent ID	20190043991
Inventor/Author	Tan Shyue Seng Quek Kiok Boone Elgin Toh Eng Huat
IPC	H01L29/788 H01L29/08 H01L29/423 H01L29/51 H01L29/66 H01L29/78
Status	Discontinued
Owner	Globalfoundries Singapore Pte. Ltd
Simple Family	011-693-210-352-738
CPC (with Group)	H10D64/033 H10D64/035 H10D30/6891 H01L21/28518 H10D30/681 H10D30/0411 H10D30/0415 H10D62/151 H10D64/514 H10D64/689 H10D30/701 H10D64/62
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent Application Publication