Oled Pixel Driving Circuit, Oled Display Panel, and Driving Method

Content Provider	The Lens
Abstract	An OLED pixel driving circuit includes a first TFT having gate connected to a third node, and having a source and a drain connected to a second node and a first node respectively; a second TFT, having gate receiving a scan signal, and having a source and a drain connected to the first node and the third node respectively; a third TFT, having gate receiving the scan signal, and having a source and a drain connected to the second node and utilized for inputting a data voltage respectively; a fourth TFT, having gate receiving an illumination signal, and having a source and a drain connected to the second node and a DC high voltage power source respectively; a fifth TFT, having gate receiving the illumination signal, and having a source and a drain connected to the first node and an anode of an OLED, and two capacitors.
Related Links	https://www.lens.org/lens/patent/011-587-319-762-117/frontpage
Language	English
Publisher Date	2019-02-19
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2017-11-30
Agent	Hauptman Ham, Llp
Applicant	Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd
Application No.	201715741865
Claim	An OLED pixel driving circuit, comprising: a first thin film transistor (TFT), having a gate electrode thereof connected to a third node, and having a source electrode and a drain electrode thereof connected to a second node and a first node respectively; a second TFT, having a gate electrode thereof receiving a scan signal, and having a source electrode and a drain electrode thereof connected to the first node and a third node respectively; a third TFT, having a gate electrode thereof receiving the scan signal, and having a source electrode and a drain electrode thereof connected to the second node and utilized for inputting a data voltage respectively; a fourth TFT, having a gate electrode thereof receiving an illumination signal, and having a source electrode and a drain electrode thereof connected to the second node and a DC high voltage power source respectively; a fifth TFT, having a gate electrode thereof receiving the illumination signal, and having a source electrode and a drain electrode thereof connected to the first node and an anode of an OLED, and the OLED having a cathode thereof connected to a DC low voltage power source; a first capacitor, having two ends connected to the second node and the third node respectively; and a second capacitor, having two ends connected to the third node and grounded respectively; wherein the first TFT is a P-type transistor, and the second TFT, the third TFT, the fourth TFT, and the fifth TFT are N-type transistors. The OLED pixel driving circuit of claim 1 , wherein a timing arrangement of the scan signal and the illumination signal includes a data storing and threshold compensation stage and an illumination stage. The OLED pixel driving circuit of claim 2 , wherein during the data storing and threshold compensation stage, the scan signal is at a high level, and the illumination signal is at a low leve The OLED pixel driving circuit of claim 2 , wherein during the illumination stage, the scan signal is at a low level, and the illumination signal is at a high leve An OLED display panel, comprising the OLED pixel driving circuit of claim 1 . A driving method for the OLED pixel driving circuit of claim 1 , comprising: arranging a timing of the scan signal and the illumination signal to include a data storing and threshold compensation stage and an illumination stage. The driving method of claim 6 , wherein during the data storing and threshold compensation stage, the scan signal is at a high level, and the illumination signal is at a low leve The driving method of claim 6 , wherein during the illumination stage, the scan signal is at a low level, and the illumination signal is at a high leve
CPC Classification	ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
Examiner	Abhishek Sarma
Extended Family	011-587-319-762-117 196-053-949-586-464 036-969-594-484-247 060-787-208-868-828
Patent ID	10210810
Inventor/Author	Wang Shan Chen Xiaolong
IPC	G09G3/3258
Status	Active
Owner	Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd
Simple Family	011-587-319-762-117
CPC (with Group)	G09G3/3233 G09G2300/0819 G09G2300/0852 G09G2300/0861 G09G2310/0262 G09G3/3258 G09G2310/08 G09G2320/0233 G09G2320/045
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent/Patent 1st level of publication/Inventor's certificate