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Bypass Circuitry for Memory Applications
| Content Provider | The Lens |
|---|---|
| Abstract | Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit. |
| Related Links | https://www.lens.org/lens/patent/011-538-331-297-608/frontpage |
| Language | English |
| Publisher Date | 2019-09-17 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2018-02-23 |
| Agent | Pramudji Law Group Pllc Ari Pramudji |
| Applicant | Advanced Risc Mach Ltd |
| Application No. | 201815904292 |
| Claim | An integrated circuit, comprising: core circuitry having an array of bitcells, wherein columns of bitcells represent bits, wherein a first column of bitcells represents a nearest bit of the bits, and wherein a last column of bitcells represents a farthest bit of the bits; sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells; multiplexer circuitry coupled to the sense amplifier circuitry; control circuitry coupled to the sense amplifier circuitry and the multiplexer circuitry, wherein the last column of bitcells is farther away from the control circuitry than the first column of bitcells such that the farthest bit of the bits is farther away from the control circuitry than the nearest bit of the bits; first bypass circuitry coupled to an output of the sense amplifier circuitry at the farthest bit so as to receive an output signal from the sense amplifier circuitry and provide an output data signal based on the output signal from the sense amplifier circuitry; and second bypass circuitry coupled to the multiplexer circuitry at the nearest bit. The integrated circuit of claim 1 , wherein the first bypass circuitry is activated based on a first bypass control signal provided by the control circuitry. The integrated circuit of claim 2 , wherein the second bypass circuitry is activated based on a second bypass control signal provided by the control circuitry, and wherein the second bypass control signal is different from the first bypass control signa The integrated circuit of claim 1 , wherein the first bypass circuitry comprises a transistor and a tristate inverter having a latch. The integrated circuit of claim 4 , wherein the transistor is coupled between the sense amplifier circuitry and the tristate inverter. The integrated circuit of claim 4 , wherein the transistor passes a data signal based on a first bypass control signa The integrated circuit of claim 4 , wherein the sense amplifier circuitry and the tristate inverter operate based on a sense amplifier enable signa The integrated circuit of claim 1 , wherein the second bypass circuitry comprises a logic gate that receives a first bypass control signal and a second bypass control signal that is different than the first bypass control signa The integrated circuit of claim 8 , wherein the logic gate comprises a NOR gate. The integrated circuit of claim 8 , wherein the second bypass circuitry provides a selection control signal to the multiplexer circuitry based on the first bypass control signal and the second bypass control signa The integrated circuit of claim 10 , wherein the multiplexer circuitry provides an output signal at an output thereof based on the outputs of the sense amplifier circuitry, a data signal, and the selection control signa An integrated circuit, comprising: memory circuitry having multiple banks of bitcells, wherein each bank of bitcells has columns of bitcells that represent bits, wherein each bank of bitcells has a first column of bitcells that represents a nearest bit of the bits, and wherein each bank of bitcells has a last column of bitcells that represents a farthest bit of the bits; multiple local input/output (IO) circuits, wherein each local IO circuit includes sense amplifier circuitry coupled to corresponding banks of the multiple banks of bitcells to assist with accessing data in the memory circuitry; a global IO multiplexer circuit having multiple multiplexer circuits coupled to outputs of corresponding sense amplifiers of the multiple local IO circuits; a global control circuit coupled to the multiple multiplexer circuits of the global IO multiplexer circuit, wherein the last column of bitcells of an upper bank is farther away from the global control circuit than the first column of bitcells such that the farthest bit of the bits is farther away from the global control circuit than the nearest bit of the bits; first bypass circuitry coupled to the sense amplifier circuitry at the farthest bit of the farthest bank to receive an output signal from the sense amplifier circuitry and provide an output data signal based on the output signal from the sense amplifier circuitry; and second bypass circuitry coupled to the global IO multiplexer circuit at the nearest bit. The integrated circuit of claim 12 , further comprising: multiple local control circuits coupled to corresponding sense amplifier circuitry of the local IO circuits. The integrated circuit of claim 13 , wherein the first bypass circuitry is activated based on a first bypass control signal provided by the multiple local control circuits and/or the global control circuit. The integrated circuit of claim 14 , wherein the second bypass circuitry is activated based on a second bypass control signal provided by the global control circuit, and wherein the second bypass control signal is different from the first bypass control signa The integrated circuit of claim 15 , wherein: the first bypass circuitry has a transistor and a tristate inverter with a latch, the transistor passes a data signal based on a first bypass control signal, the second bypass circuitry has a logic gate that receives the first bypass control signal and a second bypass control signal that is different than the first bypass control signal, and the second bypass circuitry provides a selection control signal to the multiple multiplexer circuits based on the first bypass control signal and the second bypass control signa A method of fabricating an integrated circuit, comprising: fabricating core circuitry with an array of bitcells, wherein columns of bitcells represent bits, wherein a first column of bitcells represents a nearest bit of the bits, and wherein a last column of bitcells represents a farthest bit of the bits; fabricating sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells; fabricating multiplexer circuitry coupled to the sense amplifier circuitry; fabricating control circuitry coupled to the sense amplifier circuitry and the multiplexer circuitry, wherein the last column of bitcells is farther away from the control circuitry than the first column of bitcells such that the farthest bit of the bits is farther away from the control circuitry than the nearest bit of the bits; fabricating first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit to receive an output signal from the sense amplifier circuitry and provide an output data signal based on the output signal from the sense amplifier circuitry; and fabricating second bypass circuitry coupled to the multiplexer circuitry at the nearest bit. |
| CPC Classification | STATIC STORES |
| Examiner | Vanthu T Nguyen |
| Extended Family | 011-538-331-297-608 029-858-302-490-616 177-272-320-449-658 168-426-372-403-064 108-153-638-332-455 107-395-485-727-59X 182-598-249-483-597 |
| Patent ID | 10418124 |
| Inventor/Author | Asthana Vivek Jindal Nitin Banik Saikat Kumar |
| IPC | G11C7/06 G11C7/10 G11C8/06 G11C8/12 G11C16/04 G11C29/00 G11C29/12 G11C29/14 G11C29/28 G11C29/56 |
| Status | Active |
| Owner | Arm Limited |
| Simple Family | 011-538-331-297-608 029-858-302-490-616 177-272-320-449-658 168-426-372-403-064 108-153-638-332-455 107-395-485-727-59X 182-598-249-483-597 |
| CPC (with Group) | G11C29/1201 G11C11/419 G11C7/06 G11C7/1012 G11C29/54 G11C7/12 G11C7/18 G11C29/32 G11C2029/1204 G11C7/065 G11C8/06 G11C8/12 G11C29/56012 G11C29/28 G11C29/84 G11C16/04 G11C29/14 G11C29/848 G11C29/12 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent/Patent 1st level of publication/Inventor's certificate |
