Integrated Schottky Diode in High Voltage Semiconductor Device

Content Provider	The Lens
Abstract	This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.
Related Links	https://www.lens.org/lens/patent/011-062-164-841-969/frontpage
Language	English
Publisher Date	2019-01-08
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2018-01-23
Agent	Bo-in Lin
Applicant	Alpha & Omega Semiconductor
Application No.	201815878381
Claim	A super-junction semiconductor power device disposed in an epitaxial layer supported on in a semiconductor substrate comprises an active cell area and a termination area further comprising: a gate comprises a patterned polysilicon layer disposed on a top surface of the epitaxial layer; a patterned field oxide layer disposed in said termination area and also in the active cell area at a gap area away from said patterned polysilicon layer on top of the epitaxial layer substrate; doped body regions disposed in the epitaxial layer substantially diffused from a region aligned with the gap area below the top surface and extended to regions below the patterned polysilicon layer and the patterned field oxide layer; a plurality of doped columns each vertically extended from the body regions into the epitaxial layer wherein the epitaxial layer and the semiconductor substrate having a first conductivity type and the doped columns having a second conductivity type; and doped source regions encompassed in and having an opposite conductivity type from said body regions; and a high concentration body-dopant region encompassed in each of the body regions and having a higher dopant concentration than said body region surrounding the source regions. The super-junction semiconductor power device of claim 1 further comprising: a patterned Schottky metal layer covering an area previously occupied by said field oxide layer in said active cell area and subsequently removed from on said top surface of said semiconductor substrate wherein said patterned Schottky metal layer further extends partially into said gap areas for contacting said body regions and said source regions to form integrated Schottky diodes for said semiconductor power device in said active cell area. The super-junction semiconductor power device of claim 2 further comprising: shallow body-dopant regions disposed adjacent to the body regions immediately under said Schottky metal layer having a depth significantly shallower than said body regions. The super-junction semiconductor power device of claim 2 wherein: the epitaxial layer is an N-type epitaxial layer for supporting the body-dopant regions of a P-type conductivity encompassing the source regions of the N-type conductivity therein. The super-junction semiconductor power device of claim 2 wherein: the epitaxial layer is an P-type epitaxial layer for supporting the body-dopant regions of an N-type conductivity encompassing the source regions of the P-type conductivity therein. The super-junction semiconductor power device of claim 2 wherein: the semiconductor power device further comprises a MOSFET power device. The super junction semiconductor power device of claim 2 wherein: said semiconductor power device further comprises an N-channel MOSFET power device supported on an N-type semiconductor substrate. The super junction semiconductor power device of claim 2 wherein: said semiconductor power device further comprises a P-channel MOSFET power device supported on a P-type semiconductor substrate. The super junction semiconductor power device of claim 2 wherein: said semiconductor power device further comprises an insulate gate bipolar transistor (IGBT) power device. The super junction semiconductor power device of claim 2 wherein: said semiconductor power device further comprises an insulate gate bipolar transistor (IGBT) power device supported on a N-type semiconductor substrate includes a P-type bottom layer with N-type dopant regions disposed near a bottom surface of said semiconductor substrate corresponding to said integrated Schottky diodes in said active cell area. The super junction semiconductor power device of claim 2 wherein: the plurality of doped columns are P-type doped columns extended from the body regions of the P-type conductivity into an N-type epitaxial layer.
Examiner	Chuong A Luu
Extended Family	009-888-169-065-507 011-062-164-841-969 125-481-136-333-801 177-233-524-474-335 074-352-974-569-355 072-356-964-730-796 143-488-684-634-845 050-483-624-217-48X 152-551-736-391-52X 089-275-225-986-723 092-046-161-360-797 017-903-476-296-076
Patent ID	10177221
Inventor/Author	Guan Lingpeng Bhalla Anup Bobde Madhur Zhu Tinggang
IPC	H01L29/78 H01L29/06 H01L29/08 H01L29/10 H01L29/40 H01L29/423 H01L29/49 H01L29/51 H01L29/66 H01L29/739 H01L29/872
Status	Active
Simple Family	152-551-736-391-52X 011-062-164-841-969 177-233-524-474-335 074-352-974-569-355 089-275-225-986-723 143-488-684-634-845
CPC (with Group)	H10D62/106 H10D62/111 H10D62/142 H10D62/393 H10D64/112 H10D64/516 H10D64/683 H10D12/032 H10D12/441 H10D84/146 H10D30/665 H10D8/60 H10D12/411 H10D30/0291 H10D64/661
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent/New European patent specification (amended specification after opposition procedure)