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Semiconductor Package for Thermal Dissipation
| Content Provider | The Lens |
|---|---|
| Abstract | A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks. |
| Related Links | https://www.lens.org/lens/patent/010-834-443-871-432/frontpage |
| Language | English |
| Publisher Date | 2019-05-02 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2018-12-21 |
| Applicant | Taiwan Semiconductor Mfg Co Ltd |
| Application No. | 201816230965 |
| Claim | A semiconductor device comprising: an integrated fan out package; signal connections electrically coupled to a front side of the integrated fan out package; power/ground connections electrically and physically coupled to the front side of the integrated fan out package, the power/ground connections comprising a material having a higher thermal conductivity than the signal connections; and a first substrate bonded to the integrated fan out package by the signal connections and the power/ground connections. The semiconductor device of claim 1 , wherein the signal connections comprise a different conductive material than the power/ground connections. The semiconductor device of claim 1 , wherein the signal connections are a different shape than the power/ground connections. The semiconductor device of claim 1 , wherein the integrated fan out package comprises: a first semiconductor die surrounded by an encapsulant; vias through the encapsulant and laterally spaced apart from the first semiconductor die; and metallization layers on a first side of the first semiconductor die, the metallization layers including a signal region and a power/ground region. The semiconductor device of claim 4 , wherein the signal connections are electrically coupled to the first semiconductor die and the vias. The semiconductor device of claim 4 , wherein the power/ground connections are electrically coupled to only the first semiconductor die. The semiconductor device of claim 4 , wherein the signal connections are physically coupled to the signal region of the metallization layers, and wherein the power/ground connections are physically coupled to the power/ground region of the metallization layers. The semiconductor device of claim 4 , wherein the signal region of the metallization layers includes signal vias and the power/ground region of the metallization layers includes power/ground vias, and wherein the signal vias have different diameters than the power/ground vias. The semiconductor device of claim 1 , further comprising: a second substrate bonded to a second side of the integrated fan out package, the second substrate electrically coupled to the first substrate with the signal connections. A semiconductor device comprising: an integrated fan out package, the integrated fan out package comprising an embedded die and a redistribution structure electrically coupled to the embedded die, the embedded die being disposed on a back side of the redistribution structure; first signal connectors disposed on a front side of the redistribution structure, the first signal connectors electrically coupled to the embedded die, the first signal connectors comprising a first material; first power/ground connectors disposed on the front side of the redistribution structure, the first power/ground connectors electrically coupled to the embedded die, the first power/ground connectors comprising a second material, the second material having a higher thermal conductivity than the first material; and a first substrate bonded to the first signal connectors and the first power/ground connectors. The semiconductor device of claim 10 , wherein the first signal connectors have a different size than the first power/ground connectors. The semiconductor device of claim 10 , wherein the first signal connectors are laterally separated from the first power/ground connectors. The semiconductor device of claim 10 , wherein the redistribution structure comprises a plurality of metallization layers disposed, wherein the first signal connectors and the first power/ground connectors are each physically coupled to a top metallization layer of the plurality of metallization layers. The semiconductor device of claim 13 , wherein the first signal connectors are physically coupled to a signal region of the plurality of metallization layers, and wherein the first power/ground connectors are physically coupled to a power/ground region of the plurality of metallization layers. The semiconductor device of claim 14 , wherein the signal region of the metallization layers includes signal vias and the power/ground region of the metallization layers includes power/ground vias, and wherein the signal vias have different diameters than the power/ground vias. A semiconductor device comprising: a die embedded in an encapsulant; a plurality of vias laterally separated from the embedded die by the encapsulant; a redistribution structure electrically coupled to the embedded die, the embedded die being disposed on a back side of the redistribution structure, the redistribution structure comprising a plurality of metallization layers; a signal connector disposed on a front side of the redistribution structure, the signal connector having a first shape, the signal connector comprising a first material; a power/ground connector disposed on the front side of the redistribution structure, the power/ground connector having a second shape, the power/ground connector comprising a second material, the second shape being larger than the first shape; and a first substrate bonded to the signal connector and the power/ground connector. The semiconductor device of claim 16 , further comprising: a second set of connectors disposed at a side of the embedded die on a side of the embedded die opposite the redistribution structure, the second set of connectors electrically coupled to the embedded die by the plurality of vias; and a second substrate bonded to the second set of connectors. The semiconductor device of claim 16 , wherein the power/ground connector includes a first portion overlapping the embedded die and a second portion extending beyond lateral extents of the embedded die. The semiconductor device of claim 16 , wherein the power/ground connector comprises copper blocks, copper foil, or copper paste, and wherein the signal connector comprises solder balls. The semiconductor device of claim 16 , wherein the power/ground connector includes slots disposed within the power/ground connector. |
| CPC Classification | Semiconductor Devices Not Covered By Class H10 |
| Extended Family | 027-443-150-553-800 122-720-155-702-269 124-349-877-131-823 005-712-514-058-291 181-440-217-358-656 171-642-706-708-779 089-888-541-579-670 080-139-945-447-855 010-834-443-871-432 075-948-428-459-240 044-388-643-555-115 091-656-974-190-15X |
| Patent ID | 20190131280 |
| Inventor/Author | Yu Chen-hua Jeng Shin-puu Yeh Der-chyang Chen Hsien-wei Hsieh Cheng-chieh Chiu Ming-yen |
| IPC | H01L25/065 H01L21/48 H01L21/56 H01L23/31 H01L23/367 H01L23/498 H01L25/10 |
| Status | Active |
| Simple Family | 027-443-150-553-800 122-720-155-702-269 124-349-877-131-823 005-712-514-058-291 181-440-217-358-656 171-642-706-708-779 089-888-541-579-670 080-139-945-447-855 010-834-443-871-432 075-948-428-459-240 044-388-643-555-115 091-656-974-190-15X |
| CPC (with Group) | H01L23/3128 H01L21/568 H01L23/3677 H01L23/49811 H01L23/49816 H01L23/49838 H01L23/5389 H01L24/03 H01L24/05 H01L24/08 H01L24/80 H01L25/105 H01L25/16 H01L2224/0345 H01L2224/0361 H01L2224/05624 H01L2224/05647 H01L2224/08225 H01L2224/80006 H01L2224/80904 H01L2224/9202 H01L2924/15311 H01L2924/181 H01L2924/18161 H01L25/0657 H01L21/4853 H01L23/3675 H01L2225/06517 H01L2225/0652 H01L2225/06548 H01L2225/06555 H01L2225/06572 H01L2225/06589 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent Application Publication |
