Stacked Semiconductor Die Architecture with Multiple Layers of Disaggregation

Content Provider	The Lens
Description	L'invention concerne des architectures de puces semi-conductrices empilées ayant une ou plusieurs puces de base et des techniques de formation de telles architectures. Les architectures de puces semi-conductrices empilées peuvent être incluses dans ou utilisées pour former des boîtiers de semi-conducteur. Une architecture de puces semi-conductrices empilées peut comprendre : (i) une ou plusieurs puces de base (par exemple, au moins une puce de base désagrégée, au moins une puce de base monolithique, etc.); et (ii) une tranche de support ayant de multiples puces semi-conductrices empilées incorporées dans la tranche de support, la tranche de support étant sur l'une ou plusieurs puces de base et où une ou plusieurs structures d'interconnexion (par exemple, fils, bosses, microbosses, piliers, etc.) couplent l'une ou plusieurs puces de base à la tranche de support et/ou aux puces semi-conductrices empilées.
Abstract	Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.
Related Links	https://www.lens.org/lens/patent/010-661-881-329-472/frontpage
Language	English
Publisher Date	2019-07-11
Access Restriction	Open
Alternative Title	Architecture De Puces Semi-conductrices Empilées Avec De Multiples Couches De Désagrégation
Content Type	Text
Resource Type	Patent
Date Applied	2018-01-03
Agent	Abdullahi, Abdullahi Et Al.
Applicant	Intel Corp Burton Edward
Application No.	2018012170
Claim	CLAIMS What is claimed is: A stacked semiconductor architecture for a semiconductor package, comprising: one or more base dies; and a carrier wafer on the one or more base dies, the carrier wafer including a plurality of dies, wherein one or more interconnect structures couple the plurality of dies and the one or more base dies to each other. The stacked semiconductor architecture of claim 1, wherein the carrier wafer has a surface area that exceeds a total surface area of the one or more base dies. The stacked semiconductor architecture of any one of claims 1-2, wherein the one or more base dies comprises a plurality of base dies and wherein one or more interconnect structures couple the carrier wafer to the plurality of base dies. The stacked semiconductor architecture of claim 1-2, wherein at least one of the plurality of dies in the carrier wafer are coupled to at least one of the one or more base dies with one or more microbumps. The stacked semiconductor architecture of any one of claims 1-2, wherein the one or more base dies comprise one or more of: (i) at least one monolithic base die; and (ii) at least one disaggregated base die. The stacked semiconductor architecture of any one of claims 1-2, wherein each of the plurality of dies in the carrier wafer is coupled to another one of the plurality of dies in the carrier wafer using an interconnect structure. The stacked semiconductor architecture of any one of claims 1-2, wherein top sides of the dies in the carrier wafer are co-planar with a top side of the carrier wafer. The stacked semiconductor architecture of any one of claims 1-2, wherein at least one of the plurality of dies in the carrier wafer is a memory die. A method of forming a stacked semiconductor architecture for a semiconductor package, comprising: disposing a carrier wafer on one or more base dies, the carrier wafer including a plurality of dies, wherein one or more interconnect structures couple the plurality of dies to the one or more base dies. The method of claim 10, wherein the carrier wafer has a surface area that exceeds a total surface area of the one or more base dies. The method of any one of claims 9-10, wherein the one or more base dies comprises a plurality of base dies and wherein one or more interconnect structures couple the carrier wafer to the plurality of base dies. The method of claims 9-10, wherein at least one of the plurality of dies in the carrier wafer are coupled to at least one of the one or more base dies with one or more microbumps. The method of any one of claims 9-10, wherein the one or more base dies comprise one or more of: The method of any one of claims 9-10, wherein each of the plurality of dies in the carrier wafer is coupled to another one of the plurality of dies in the carrier wafer using an interconnect structure. The method of any one of claims 9-10, wherein top sides of the dies in the carrier wafer are co-planar with a top side of the carrier wafer. The method of any one of claims 9-10, wherein at least one of the plurality of dies in the carrier wafer is a memory die. The method of any one of claims 9-10, further comprising: forming cavities in the carrier wafer; and placing the plurality of dies in the cavities. The method of claim 17, further comprising bonding the plurality of dies to the carrier wafer. 19. The method of claim 17, further comprising planarizing a top side of the carrier wafer and at least one top side of the plurality of dies in the carrier wafer. The method of any one of claims 9-10 and 18-19, further comprising, for each of the one or more base dies, forming one or more microbumps on a top side of the disaggregated base die.
CPC Classification	Semiconductor Devices Not Covered By Class H10
Extended Family	043-278-890-724-664 039-830-594-450-197 158-761-900-226-854 010-661-881-329-472 166-442-217-655-664 175-752-435-497-107 102-849-604-496-248 164-600-158-478-706
Patent ID	2019135739
Inventor/Author	Burton Edward
IPC	H01L25/065 H01L23/00 H01L23/04 H01L25/18
Status	Pending
Simple Family	043-278-890-724-664 039-830-594-450-197 158-761-900-226-854 010-661-881-329-472 166-442-217-655-664 175-752-435-497-107 102-849-604-496-248 164-600-158-478-706
CPC (with Group)	H01L25/18 H01L2224/16145 H01L2224/16225 H01L2924/37001 H01L2225/06513 H01L2225/06517 H01L25/50 H01L2924/15153 H01L2924/1434 H01L25/0652 H01L24/16 H01L25/00
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent Application Publication