Method for Driving A Display Panel, Display Panel, and Display Device

Content Provider	The Lens
Abstract	A method for driving a display panel, a display panel, and a display device are provided, where in a first operating mode, a gate driver circuit is controlled for each image frame to output a scan signal to N rows of gate lines on the display panel sequentially in a preset scan direction to thereby display throughout a screen; and in a second operating mode, the gate driver circuit is controlled for each image frame to output a scan signal to m adjacent rows of gate lines on the display panel sequentially in the preset scan direction to thereby display only in an area corresponding to the m adjacent rows of gate lines without scanning the gate lines in an area in which no image may be displayed, so as to lower power consumption of the display panel operating in the second operating mode.
Related Links	https://www.lens.org/lens/patent/010-271-125-014-340/frontpage
Language	English
Publisher Date	2019-03-26
Access Restriction	Open
Content Type	Text
Resource Type	Patent
Jurisdiction	United States of America
Date Applied	2017-11-01
Agent	Kilpatrick Townsend & Stockton Llp
Applicant	Wuhan Tianma Micro Electronics Co Ltd
Application No.	201715800091
Claim	A display panel, comprising: a gate driver circuit; a timing controller; a mode switching circuit; N rows of gate lines, wherein N is the total number of rows of gate lines on the display panel; the gate driver circuit is connected with the N rows of gate lines, and configured to be controlled by the timing controller to output a scan signal to the gate lines; the mode switching circuit is configured to transmit a first mode control signal to the timing controller in a first operating mode, and a second mode control signal to the timing controller in a second operating mode; the timing controller is configured to control the gate driver circuit for each image frame to sequentially output a scan signal to the N rows of gate lines on the display panel in a preset scan direction upon reception of the first mode control signal; and to control the gate driver circuit for each image frame to sequentially output a scan signal to m adjacent rows of gate lines on the display panel in the preset scan direction upon reception of the second mode control signal, wherein m is a predetermined integer greater than 0 and less than N; and wherein the gate driver circuit comprises concatenated N levels of shift registers, an output terminal of each level of the shift registers other than first level of shift register is connected with an end terminal of a preceding level of shift register, and the output terminal of each level of the shift registers other than last level of shift register is connected with an input terminal of a succeeding level of shift register; and the display panel further comprises a first trigger signal line connected between the first level of shift register and the timing controller and a second trigger signal line connected between the a-th level of shift register and the timing controller. The display panel according to claim 1 , wherein each level of the shift registers corresponds to one row of gate lines on the display panel and the a-th level of shift register to the b-th level of shift register correspond to the m adjacent rows of gate lines on the display panel; and the timing controller is configured to transmit a frame trigger signal to the first level of shift register in the gate driver circuit for each image frame to trigger the N levels of the shift registers to output a scan signal sequentially, upon reception of the first mode control signal; and transmit a frame trigger signal to the a-th level of shift register in the gate driver circuit for each image frame to trigger the a-th level of shift register to the b-th level of shift register to output a scan signal sequentially, upon reception of the second mode control signa The display panel according to claim 2 , wherein the timing controller transmits the frame trigger signal to the first level of shift register over the first trigger signal line connected between the first level of shift register and the timing controller; and the timing controller transmits the frame trigger signal to the a-th level of shift register over the second trigger signal line connected between the a-th level of shift register and the timing controller. The display panel according to claim 2 , wherein the timing controller is further configured: after the frame trigger signal is transmitted to the a-th level of shift register, and the b-th level of shift register outputs the scan signal, to transmit a reset signal to the (b+1)-th level of shift register. The display panel according to claim 4 , wherein the timing controller is further configured to transmit the reset signal to other levels of shift registers at the same time when the reset signal is transmitted to the (b+1)-th level of shift register. The display panel according to claim 2 , wherein the timing controller is further configured: after the frame trigger signal is transmitted to the a-th level of shift register, and the b-th level of shift register outputs the scan signal, to convert a clock signal transmitted to the gate driver circuit into a direct-current signa The display panel according to claim 2 , wherein the timing controller is further configured: after the first mode control signal or the second mode control signal is received, and before the frame trigger signal is transmitted to the gate driver circuit for each image frame, to transmit a reset signal to each level of the shift registers. The display panel according to claim 1 , wherein the timing controller is further configured to: control the gate driver circuit upon reception of the first mode control signal to sequentially output a scan signal to the N rows of gate lines on the display panel at a first refresh frequency; and control the gate driver circuit upon reception of the second mode control signal to sequentially output a scan signal to the m adjacent rows of gate lines on the display screen at a second refresh frequency, wherein the second refresh frequency is smaller than or equal to the first refresh frequency. The display panel according to claim 8 , wherein the timing controller controls a refresh frequency of the gate driver circuit by controlling a clock signal transmitted to the gate driver circuit, and shorter a clock periodicity at which the clock signal is transmitted to the gate driver circuit by the timing controller is, higher the refresh frequency of the gate driver circuit is. The display panel according to claim 2 , wherein in the gate driver circuit, a reset terminal of each level of the shift registers is connected with the same reset signal line. A display device, comprising: a display panel; a gate driver circuit; a timing controller; a mode switching circuit; N rows of gate lines, wherein N is the total number of rows of gate lines on the display panel; the gate driver circuit is connected with the N rows of gate lines, and configured to be controlled by the timing controller to output a scan signal to the gate lines; the mode switching circuit is configured to transmit a first mode control signal to the timing controller in a first operating mode, and a second mode control signal to the timing controller in a second operating mode; the timing controller is configured to control the gate driver circuit for each image frame to sequentially output a scan signal to the N rows of gate lines on the display panel in a preset scan direction upon reception of the first mode control signal and control the gate driver circuit for each image frame to sequentially output a scan signal to m adjacent rows of gate lines on the display panel in the preset scan direction upon reception of the second mode control signal, wherein m is a predetermined integer greater than 0 and less than N; and wherein the gate driver circuit comprises concatenated N levels of shift registers, an output terminal of each level of the shift registers other than first level of shift register is connected with an end terminal of a preceding level of shift register, and the output terminal of each level of the shift registers other than last level of shift register is connected with an input terminal of a succeeding level of shift register; and the display panel further comprises a first trigger signal line connected between the first level of shift register and the timing controller and a second trigger signal line connected between the a-th level of shift register and the timing controller. A method for driving a display panel, the method comprising: performing a first operating mode in which a gate driver circuit is controlled for each image frame to sequentially output a scan signal to N rows of gate lines on the display panel in a preset scan direction, wherein N is the total number of rows of gate lines on the display panel; performing a second operating mode in which the gate driver circuit is controlled for each image frame to sequentially output a scan signal to m adjacent rows of gate lines on the display panel in the preset scan direction, wherein m is a predetermined integer greater than 0 and less than N; and wherein the gate driver circuit comprises concatenated N levels of shift registers, an output terminal of each level of the shift registers other than first level of shift register is connected with an end terminal of a preceding level of shift register, and the output terminal of each level of the shift registers other than last level of shift register is connected with an input terminal of a succeeding level of shift register; and the display panel further comprises a timing controller, a first trigger signal line connected between the first level of shift register and the timing controller, and a second trigger signal line connected between the a-th level of shift register and the timing controller. The driving method according to claim 12 , wherein each level of the shift registers corresponds to one row of gate lines on the display panel and the a-th level of shift register to the b-th level of shift register correspond to the m adjacent rows of gate lines on the display panel; and the driving method comprises: performing the first operating mode in which a frame trigger signal is transmitted to the first level of shift register in the gate driver circuit for each image frame to trigger the N levels of the shift registers to sequentially output a scan signal; and performing the second operating mode in which a frame trigger signal is transmitted to the a-th level of shift register in the gate driver circuit for each image frame to trigger the a-th level of shift register to the b-th level of shift register to sequentially output a scan signa The method according to claim 13 , wherein after the frame trigger signal is transmitted to the a-th level of shift register, and the b-th level of shift register outputs the scan signal, the method further comprises: transmitting a reset signal to (b+1)-th level of shift register. The method according to claim 14 , wherein at the same time when the reset signal is transmitted to the (b+1)-th level of shift register, the method further comprises: transmitting the reset signal to other levels of shift registers. The method according to claim 13 , wherein after the frame trigger signal is transmitted to the a-th level of shift register, and the b-th level of shift register outputs the scan signal, the method further comprises: converting a clock signal transmitted to the gate driver circuit into a direct-current signa The method according to claim 13 , wherein before the frame trigger signal is output to the gate driver circuit for each image frame, the method further comprises: transmitting a reset signal to each level of the shift registers. The method according to 12 , wherein in the first operating mode, the gate driver circuit is controlled to output a scan signal to the N rows of gate lines on the display panel sequentially at a first refresh frequency; and the gate driver circuit is controlled to sequentially output a scan signal to the m adjacent rows of gate lines on the display screen at a second refresh frequency, wherein the second refresh frequency is smaller than or equal to the first refresh frequency. The method according to claim 18 , wherein the refresh frequency of the gate driver circuit is controlled by controlling the clock signal transmitted to the gate driver circuit, and shorter a clock periodicity at which the clock signal is transmitted to the gate driver circuit by the timing controller is, higher the refresh frequency of the gate driver circuit is.
CPC Classification	ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION STATIC STORES
Examiner	Richard J Hong
Extended Family	008-545-287-575-961 010-271-125-014-340 114-687-101-823-303
Patent ID	10242613
Inventor/Author	Lu Qing Zeng Min Ma Xiaomeng
IPC	G09G3/20 G09G5/00 H01L27/12
Status	Active
Owner	Wuhan Tianma Micro-electronics Co. Ltd
Simple Family	008-545-287-575-961 010-271-125-014-340 114-687-101-823-303
CPC (with Group)	G09G3/20 G11C19/28 G09G2310/0286 G09G2310/0267 G09G2310/04 G09G2330/021 G09G2300/08 G09G3/2092 G09G3/2022 G09G5/003 G09G2310/0283 G09G2310/0243 G09G2300/0408 H10D86/60 H10D86/441
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent/New European patent specification (amended specification after opposition procedure)