Crystal Orientation Engineering to Achieve Consistent Nanowire Shapes

Content Provider	The Lens
Description	Les revendications indépendantes de ce brevet signifient une description concise des modes de réalisation. L'invention concerne une technologie, grossièrement décrite, dans laquelle une structure semi-conductrice comprend un substrat supportant une colonne d'au moins un (et de préférence de plus d'un) transistor à nanofeuilles orienté horizontalement, chacun ayant un segment de canal respectif de matériau de nanofeuille cristallin semi-conducteur (de préférence du silicium ou un alliage de silicium) gainé par un matériau d'empilement de grille, les segments de canal ayant une structure de cristal cubique de diamant et étant orientés de telle sorte que les plans {111} soient horizontaux. La présente invention porte également sur un procédé permettant de fabriquer une telle structure, et sur un substrat ondulé qui peut être formé en tant que produit intermédiaire. Cet abrégé n'est pas destiné à limiter la portée des revendications.
Abstract	The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a diamond cubic crystal structure and are oriented such that the {111} planes are horizontal. Also disclosed is a method for fabricating such a structure, and a corrugated substrate that may be formed as an intermediate product. This Abstract is not intended to limit the scope of the claims.
Related Links	https://www.lens.org/lens/patent/009-673-528-177-378/frontpage
Language	English
Publisher Date	2019-11-21
Access Restriction	Open
Alternative Title	Ingénierie D'orientation De Cristaux Pour Obtenir Des Formes De Nanofils Cohérentes
Content Type	Text
Resource Type	Patent
Date Applied	2019-05-13
Agent	Wolfeld, Warren S. Et Al.
Applicant	Synopsys Inc
Application No.	2019032059
Claim	CLAIMS What is claimed is: A semiconductor structure comprising: a column of at least one horizontally-oriented nanosheet transistor, each of the nanosheet transistors having a respective channel segment of semiconductor crystalline nanosheet material sheathed by gate stack material; and a substrate supporting the column, wherein the channel segments of semiconductor crystalline nanosheet material have a diamond cubic crystal structure and which is oriented such that the { 1 11 } planes of the nanosheet material are horizonta The structure of claim 1, wherein the column comprises a plurality of the nanosheet transistors The structure of claim 1, wherein the gate stack material comprises a gate conductor sheathing the channel segment of each of the nanosheet transistors and spaced from the channel segment of each of the nanosheet transistors by a gate dielectric materia The structure of claim 3, wherein each of the nanosheet transistors further includes source and drain regions disposed on opposite ends of the of the channel segments longitudinally, wherein all of the source regions are connected in parallel, all of the drain regions are connected in parallel, and all of the gate conductors are connected in paralle The structure of claim 3, further comprising a second column of at least one of the horizontally-oriented nanosheet transistors, wherein each of the nanosheet transistors further includes source and drain regions disposed on opposite ends of the of the channel segments longitudinally, 6 The structure of claim 1, wherein the semiconductor crystalline nanosheet material is silicon or a silicon alloy. A method of making a semiconductor structure, comprising: providing a substrate; and forming a column of at least one horizontally-oriented nanosheet transistor supported on the substrate, each of the nanosheet transistors having a respective channel segment of semiconductor crystalline nanosheet material sheathed by gate stack material, wherein the channel segments of semiconductor crystalline nanosheet material have a diamond cubic crystal structure and which is oriented such that { 111 } planes of the nanosheet material are horizonta The method of claim 7, wherein the column comprises a plurality of the nanosheet transistors. The method of claim 7, wherein the gate stack material comprises a gate conductor sheathing the channel segment of each of the nanosheet transistors and spaced from the channel segment of each of the nanosheet transistors by a gate dielectric materia The method of claim 9, wherein each of the nanosheet transistors further includes source and drain regions disposed on opposite ends of the of the channel segments longitudinally, 1 1. The method of claim 9, further comprising a second column of at least one of the horizontally-oriented nanosheet transistors, The method of claim 7, wherein forming a column of at least one horizontally- oriented nanosheet transistor comprises: forming on the substrate a column of layers including at least one silicon layer each spaced from a next layer below, each of the silicon layers being oriented such that { 111 } planes of the silicon layers are horizontal; annealing the column of layers to round comers of the channel segment of each of the silicon layers in the stack; and sheathing the channel segment of each of the silicon layers in the stack with the gate stack materia The method of claim 12, wherein the gate stack material comprises a gate conductor sheathing the channel segment of each of the nanosheet transistors and spaced from the channel segment of each of the nanosheet transistors by a gate dielectric material, and wherein forming a column of at least one horizontally-oriented nanosheet transistor further comprises: forming source and drain regions on opposite ends of the of the channel segments longitudinally; connecting all of the source regions in parallel; connecting all of the drain regions in parallel; and connecting all of the gate conductors in paralle The method of claim 12, wherein forming on the substrate a column of layers including at least one silicon layer each spaced from a next layer below comprises: forming on the substrate a stack of silicon layers alternating with layers of a sacrificial material, including at least one silicon layer and at least one layer of the sacrificial material below each of the silicon layers and above the substrate; patterning the stack to form a column of the alternating silicon layers and layers of the sacrificial material; and removing the sacrificial material at least below a respective channel segment of each of the silicon layers in the column. The method of claim 14, wherein the substrate has a top surface of silicon oriented such that its { 111 } planes are horizontal, wherein the sacrificial material has a diamond cubic crystal structure, and wherein forming on the substrate a stack of silicon layers alternating with layers of a sacrificial material, comprises growing the stack of layers epitaxially on the substrate. The method of claim 15, wherein the sacrificial material is SiGe. An intermediate structure comprising: a substrate; and a plurality of parallel ridges supported by the substrate, wherein each of the ridges comprises a plurality of layers of silicon alternating with layers of SiGe, including at least one silicon layer and at least one layer of SiGe below each of the silicon layers and above the substrate, and wherein the silicon layers are oriented such that the { 111 } planes are horizonta The intermediate structure of claim 17, wherein the SiGe layers are oriented such that the { 111 } planes are horizonta The intermediate structure of claim 18, wherein the substrate has a top surface of { 11 1 {-oriented silicon, and wherein the layers are formed by epitaxial growth on the substrate.
CPC Classification	Semiconductor Devices Not Covered By Class H10 SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES;MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES;MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
Extended Family	098-059-916-847-028 046-280-089-306-821 086-704-366-777-646 121-394-135-723-575 009-841-535-387-701 152-571-518-844-314 020-492-428-743-26X 009-673-528-177-378 128-649-924-211-19X
Patent ID	2019222115
Inventor/Author	Moroz Victor Martin-bragado Ignacio
IPC	H01L29/06 H01L21/02 H01L21/027 H01L21/28 H01L21/768 H01L29/41
Status	Pending
Simple Family	098-059-916-847-028 046-280-089-306-821 086-704-366-777-646 121-394-135-723-575 009-841-535-387-701 152-571-518-844-314 020-492-428-743-26X 009-673-528-177-378 128-649-924-211-19X
CPC (with Group)	H01L21/3247 B82Y10/00 H10D84/83 H10D62/405 H10D62/121 H10D30/6735 H10D30/014 H10D64/017 H10D30/0323 H10D30/43 H10D30/6757 H01L21/02603 H01L21/027 H01L21/76816 H01L21/76846 H01L21/28255 H10D62/119 H10D64/205 H01L21/02532 H01L21/30604 H01L21/02609 H10D30/031 H10D62/57
Issuing Authority	United States Patent and Trademark Office (USPTO)
Kind	Patent Application Publication