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Serializer-deserializer with Frequency Doubler
| Content Provider | The Lens |
|---|---|
| Abstract | A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data. |
| Related Links | https://www.lens.org/lens/patent/009-129-266-363-154/frontpage |
| Language | English |
| Publisher Date | 2019-01-10 |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
| Jurisdiction | United States of America |
| Date Applied | 2018-05-25 |
| Applicant | Qualcomm Inc |
| Application No. | 201815990517 |
| Claim | A system, comprising: a quarter-rate clock source configured to generate a quarter-rate clock signal and a quadrature of the quarter-rate clock signal; a first frequency doubler configured to produce a first half-rate clock signal responsive to the quarter-rate clock signal and the quadrature of the quarter-rate clock signal; and a serializer transmitter configured to serialize a parallel input data stream into a serialized data stream responsive to the first half-rate clock signal, wherein a data rate for the serialized data stream is twice a frequency for the first half-rate clock signal, and wherein the frequency for the first half-rate clock signal is twice a frequency for the quarter-rate clock signa The system of claim 1 , wherein the quarter-rate clock source, the first frequency doubler, and the serializer transmitter are integrated into an integrated circuit. The system of claim 1 , wherein the serializer transmitter is configured to sample the parallel input data stream responsive to both rising edges and falling edges for the first half-rate clock signa The system of claim 1 , wherein the quarter-rate clock source is further configured to generate an inverse of the quarter-rate clock signal and a quadrature of the inverse of the quarter-rate clock signal, and wherein the first frequency doubler is further configured to produce the first half-rate clock signal and an inverse of the first half-rate clock signal responsive to the quarter-rate clock signal, the inverse of the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signa The system of claim 4 , wherein the serializer transmitter is configured to sample the parallel input data stream responsive to rising edges of the first half-rate clock signal and to rising edges of the inverse of the first half-rate clock signa The system of claim 4 , further comprising: a second frequency doubler configured to produce a second half-rate clock signal and an inverse of the second half-rate clock signal responsive to the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, the inverse of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal; and a clock transmitter configured to transmit the second half-rate clock signal and the inverse of the second half-rate clock signa The system of claim 1 , wherein the first frequency doubler comprises an exclusive-or (XOR) gate. The system of claim 1 , further comprising a duty-cycle adjuster circuit configured to adjust a duty cycle for the first half-rate clock signal to equal a 50-50 duty cycle. The system of claim 4 , further comprising: a second frequency doubler configured to produce a second half-rate clock signal and an inverse of the second half-rate clock signal responsive to the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, the inverse of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal; a delay-locked loop configured to generate a quadrature half-rate clock signal and an inverse of the quadrature half-rate clock signal responsive to the second half-rate clock signal and the inverse of the second half-rate clock signal; and a receiver deserializer configured to deserialize a received serial data stream using an aligned clock from a clock data recovery (CDR) circuit, wherein the CDR circuit is configured to align the aligned clock responsive to the second half-rate clock signal, the inverse of the second half-rate clock signal, the quadrature half-rate clock signal, and the inverse of the quadrature half-rate clock signa The system of claim 4 , wherein the clock source is a phase-locked loop (PLL). The system of claim 10 , further comprising: a second frequency doubler configured to produce a second half-rate clock signal and an inverse of the second half-rate clock signal responsive to the quarter-rate clock signal, the inverse of the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal, wherein the quarter-rate clock signal is 0 degree phase quarter-rate clock signal, the quadrature of the quarter-rate clock signal is a 90 degree quarter-rate clock signal, the inverse of the quarter-rate clock signal is a 180 degree quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal is a 270 degree phase quarter-rate clock signal, and wherein the PLL is further configured to produce a 45 degree phase quarter-rate clock signal, a 135 degree phase quarter-rate clock signal, a 225 degree phase quarter-rate clock signal, and a 315 degree quarter-rate clock signal; and a third frequency doubler configured to produce a third half-rate clock signal and an inverse of the third half-rate clock signal responsive to the 45 degree phase quarter-rate clock signal, the 135 degree phase quarter-rate clock signal, the 225 degree phase quarter-rate clock signal, and the 315 degree quarter-rate clock signal; and a receiver deserializer configured to deserialize a received serial data stream using an aligned clock from a clock data recovery (CDR) circuit, wherein the CDR circuit is configured to align the aligned clock responsive to the second half-rate clock signal, the inverse of the second half-rate clock signal, the third half-rate clock signal, and the inverse of the third half-rate clock signa A method, comprising: generating a quarter-rate clock signal and a quadrature of the quarter-rate clock signal in a clock source within an integrated circuit; transmitting the quarter-rate clock signal and the quadrature of the quarter-rate clock signal to a first frequency doubler within the integrated circuit; generating a first half-rate clock signal in the first frequency doubler responsive to the quarter-rate clock signal and the quadrature of the quarter-rate clock signal; and serializing a parallel input data stream responsive to the first half-rate clock signal in a serializer transmitter within the integrated circuit into a serialized data stream, wherein a data rate for the serialized data stream is twice a frequency for the first half-rate clock signal, and wherein the frequency of the first half-rate clock signal is twice a frequency for the quarter-rate clock signa The method of claim 12 , wherein serializing the parallel input data stream comprises sampling the parallel input data stream responsive to both rising edges and falling edges of the first half-rate clock signa The method of claim 12 , further comprising: generating an inverse of the quarter-rate clock signal and a quadrature of the inverse of the quarter-rate clock signal in the clock source; transmitting the inverse of the quarter-rate clock signal and the quadrature of the inverse of the quarter-rate clock signal to the first frequency doubler; and generating an inverse of the first half-rate clock signal in the first frequency doubler responsive to the inverse of the quarter-rate clock signal and the quadrature of the inverse of the quarter-rate clock signal, wherein serializing the parallel input data stream in the serializer transmitter comprises sampling the parallel input data stream responsive to rising edges of the first half-rate clock signal and to rising edges of the inverse of the first half-rate clock signa The method of claim 12 , wherein the quarter-rate clock signal is a 5 GHz clock signal, and wherein the data rate is 20 GHz. The method of claim 14 , further comprising: transmitting the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, the inverse of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signal to a second frequency doubler within the integrated circuit; and generating a second half-rate clock signal and in inverse of the second half-rate clock signal in the second frequency doubler responsive to the quarter-rate clock signal, the inverse of the quarter-rate clock signal, the quadrature of the quarter-rate clock signal, and the quadrature of the inverse of the quarter-rate clock signa The method of claim 16 , further comprising: generating an inverse of the second half-rate clock signal and a quadrature of the inverse of the second half-rate clock signal within the integrated circuit; and deserializing a received serial data stream using an aligned clock, wherein aligning the aligned clock is responsive to the second half-rate clock signal, the inverse of the second half-rate clock signal, the quadrature of the second half-rate clock signal, and the quadrature of the inverse of the second half-rate clock signa An integrated circuit, comprising: a quarter-rate clock source configured to generate a quarter-rate clock signal; means for doubling a frequency of the quarter-rate clock signal to produce a first half-rate clock signal having a frequency that is twice a frequency of the quarter-rate clock signal; and a serializer transmitter configured to serialize a parallel input data stream into a serialized data stream responsive to the first half-rate clock signal, wherein a data rate for the serialized data stream is twice the frequency for the first half-rate clock signa The integrated circuit of claim 18 , wherein the clock source comprises a phase-locked loop (PLL). The integrated circuit of claim 18 , wherein the serializer transmitter is configured to sample the parallel input data stream responsive to both rising and falling edges of the first half-rate clock signa |
| CPC Classification | ELECTRIC DIGITAL DATA PROCESSING PULSE TECHNIQUE AUTOMATIC CONTROL; STARTING; SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES TRANSMISSION OF DIGITAL INFORMATION; e.g. TELEGRAPHIC COMMUNICATION |
| Extended Family | 107-382-076-952-937 114-472-356-854-840 009-129-266-363-154 |
| Patent ID | 20190013929 |
| Inventor/Author | Hailu Eskinder Pandita Bupesh Gao Zhuo |
| IPC | H04L7/033 |
| Status | Active |
| Owner | Qualcomm Incorporated |
| Simple Family | 114-472-356-854-840 107-382-076-952-937 009-129-266-363-154 |
| CPC (with Group) | G06F1/10 H03K5/00006 H03L7/16 H04L7/0331 |
| Issuing Authority | United States Patent and Trademark Office (USPTO) |
| Kind | Patent Application Publication |
