IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture

Content Provider	IEEE Xplore Digital Library (Standards)
Abstract	This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip test access ports (TAPs) specified by IEEE Std 1149.1¿-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 test access ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class TO provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire series or star scan topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher test clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.
Sponsorship	Test Technology of the IEEE Computer Society
ISBN	9780738161532
Language	English
Publisher	IEEE
Publisher Date	2010-02-10
Publisher Place	New York, NY
Access Restriction	Subscribed
Rights Holder	IEEE
Subject Keyword	IEEE standards Testing Boundary conditions zero bit scan 1149.7-2009 1149.1 1149.7 2-pin 2-wire 4-pin 4-wire Advanced Protocol Advanced Protocol Unit APU Background Data Transfer background data transport BDX boundary scan BSDL BSDL.1 BSDL.7 BYPASS Capture-IR CDX Chip-Level TAP Controller CID Class T0 Class T1 Class T2 Class T3 Class T4 Class T5 CLTAPC compact JTAG compliant behavior compliant operation control level controller address Controller ID Controller Identification Number CP Custom Data Transfer custom data transport Data Register debug interface debug logic debug and test interface DOT1 DOT7 DTI DTS DTT Debug Test System debug test target Escape EOT EPU extended operation Extended Protocol EXTEST HSDL HSDL.7 IDCODE Instruction Register JScan JScan0 JScan1 JScan2 JScan3 JTAG MScan MTCP Multi-TAP Control Path narrow Star Scan Topology nTRST nTRST_PD optimized scan OScan OScan0 OScan1 OScan2 OScan3 OScan4 OScan5 OScan6 OScan7 Pause-DR Pause-IR PC0 PC1 RSU Reset and selection unit RTI Run-Test/Idle scan scan DR scan format scan IR Scan Packet scan path scan performance scan protocol scan topology series Series Branch Series Scan Series Scan Topology Series-Equivalent Scan Series Topology Shift-DR Shift-IR SiP Star Scan Star Scan Topology Star Topology Star-2 Star-2 Branch Star-2 Scan Scan Topology Star-4 Star-4 Branch Star-4 Scan Star-4 Scan Topology SP SScan SScan0 SScan1 SScan2 SScan3 stall SSD Scan Selection Directive Standard Protocol star scan STL System Test Logic TAP TAP controller TAP controller address TAP selection TAP.1 TAP.7 TAPC TCA TCKC TDI TDIC TDOC TDOE Test Access Port test and debug Test-Logic-Reset TLR TMSC Transport Packet T0 T0 TAP.7 T1 T1 TAP.7 T2 T2 TAP.7 T3 T3 TAP.7 T4 T4 TAP.7 T4(N) T4(N) TAP.7 T4(W) T4(W) TAP.7 T5 T5 TAP.7 T5(N) T5(N) TAP.7 T5(W) T5(W) TAP.7 TP Update-DR Update-IR ZBS
Content Type	Text
Resource Type	Standard
Issuing Authority	IEEE Standards Association (IEEE SA)