NDLI: PROBLEM 11 - 0719: Sweep Circuits - TIMING CIRCUITS AND WAVEFORM GENERATORS

Content Provider	StemEZ
Description	The transistor of the Miller integrator of Fig. 1 has h$_{IE}$ = 750Ω and h$_{FE}$ = 72 Ω; h$_{RE}$ and h$_{OE}$ may be neglected. The collector is biased from a 15 volt source through load R$_{L}$ = 1000 Ω. The base is biased from a square wave generator which also performs the function of switching the sweep on and off. To minimize loading on the square wave generator by the sweep circuit, a diode is inserted in series with the base of the transistor. It may be seen from the oscillograms of the base voltage and the sweep output (Fig. 6) that the mutual loading of the two parts of the circuit has not been eliminated completely (note the overshoots and undershoots). (Because of the photographic technique used, Fig. 6 is reversed left-to-right.) During the sweep, the input is zero, the transistor is in the active region, and the circuit operates as an amplifier. When the input goes up, the transistor is driven into saturation. The capacitor discharges quickly with a very short time constant through the collector, which remains at almost zero (0.05 volts), until the input wave goes down again. Fig. 2 is the equivalent circuit of Fig. 1 when the transistor is saturated (resistor values are experimentally determined). a) Examine, quantitatively, the behavior of the circuit. b) Find the nonlinearity of the sweep. c) Calculate the fly‒back (retrace) time.
Language	English
Publisher	StemEZ.com
Access Restriction	Open
Subject Keyword	Miller Integrator
Content Type	Text
Educational Role	Student Teacher
Educational Use	Self Learning Problem Solving Reading Assessment
Resource Type	Question Set Solution
Education Level	Under Graduate Post Graduate
Subject	Applied physics

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in