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Improvement in static timing analysis for early ta-signoff closure in soc flow at very deep submicron nodes
| Content Provider | Indraprastha Institute of Information Technology, Delhi |
|---|---|
| Author | Singh, Vinod Kumar |
| Abstract | An approach is proposed to improve static timing analysis for early TA-signoff closure at Very Deep Sub-Micron (V-DSM) nodes. At higher technology nodes (>100nm) the timing path delay is governed mainly by the cells, and hence the traditional corners (PVT) are sufficient to decide proper timing and functionality of SoC. With technology scaling, the dimension of transistors and interconnects get reduced, resulting in decrease in the driving capability of cells and a simultaneous increase in the resistance of interconnects. This makes the contribution of interconnects to the path delay grow in comparison to the cell contribution. In addition, PVT variations increase with scaling, affecting the cells as well as interconnects. This results in drastic increase in timing analysis corners to achieve the desired functionality of system on chip (SoC). The growing demand of different functionalities in SoC has increased the number of modes and hence the number of analysis views (combination of modes and corners). That makes timing complex, which is further enhanced due to high frequency requirement. Timing complexity makes STA technique time-consuming. To reduce time, multiple corners run in parallel using Distributed Multi-Mode-Multi-Corners (DMMMC) technique rather than MMMC technique which is operated sequentially. As SoC size increases (size – number of instances), it becomes more and more difficult for MMMC technique to perform the job adequately. DMMMC saves time but not so significantly as number of modes also increases simultaneously. Large SoCs require each corner to be run in parallel on multiple machines, and hence cost per corner increases. To save host machine cost and machine run time, it is desired to reduce timing corners. This can be done by determining and exploiting the correlation between different parameters and their effects on timing. The proposed idea has been carried out by measuring slack variation across the available corners. Three critical corners, out of the 12 corners provided by foundry, have been determined with ± 2-5 % variation: one for hold check and two for setup check. Now STA is limited to only these critical corners before final TA-signoff. By utilising these critical corners the machine license requirement as well as the machine run time can be reduced to 25%. This results in increased productivity of the organization while maintaining quality as well, by decreasing TA- cycle for early TA-signoff. |
| File Format | |
| Language | English |
| Publisher | IIIT Delhi |
| Access Restriction | Open |
| Subject Keyword | Very Deep Sub-Micron (V-DSM) PVT system on chip (SoC) Distributed Multi-Mode-Multi-Corners (DMMMC) decreasing TA- cycle early TA-signoff |
| Content Type | Text |
| Educational Degree | Master of Technology (M.Tech.) |
| Resource Type | Thesis |
| Subject | Applied physics |
