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Executable model based design methodology for fast prototyping of mobile network protocol : a case study on mipi lli
| Content Provider | Indraprastha Institute of Information Technology, Delhi |
|---|---|
| Author | Shah, Rahul Kumar |
| Abstract | Future mobile communication systems incorporate more sophisticated functionalities which im- prove their performance and increase their complexity. In order to reduce their time to market, the RTL development as well the simulation time of the prototyping phase has to be improved. This work presents a solution for improving the prototyping time by using Model Based Design approach comprising of Simulink HDL coder, HDL Veri er and rapid FPGA prototyping by means of FPGA in loop co-simulation. As a case study, the MIPI Low Latency Interface (LLI) layer protocol is implemented. The results presented in this report demonstrate that hardware acceleration based on reduction in prototyping time can be achieved by reducing the RTL development time and simulation time needed to validate the behavior of the design under test and enabling FPGA in loop co- simulation. In this dissertation comparison of the automatic generated HDL code from the Simulink HDL coder to that of manual hand-written code is performed. The comparison targets the time to market, area, power and timing constrains for the Data Link Layer (DLL) of MIPI LLI for both the procedures. Moreover, this dissertation discusses the limitation associated with Simulink Model Based Design methodology with a test case, modeling of single cycle latency CRC algorithm. The automatic HDL code generated from the Simulink Model Based Design using MATLAB R2013a, and the manual hand-written Verilog code for the Data Link Layer are synthesized for CMOS 45 nm standard cell ASIC technology. The comparison result shows that time to market value is reduced by more than half with signi cant decrease of 11% to 17% in the operating speed, the area and power consumption also increases by 25% and 29% respectively. Keyword- Area, Data Link Layer, Executable Model Based Design, FPGA in loop, Low Latency Interface, power, Rapid prototyping, Simulink HDL coder, time to market, timing. |
| File Format | |
| Language | English |
| Publisher | IIIT Delhi |
| Access Restriction | Open |
| Subject Keyword | Area Data Link Layer Executable Model Based Design FPGA in loop Low Latency Interface, power Rapid prototyping Simulink HDL coder Time to Market Timing |
| Content Type | Text |
| Educational Degree | Master of Technology (M.Tech.) |
| Resource Type | Thesis |
| Subject | Applied physics |
